See Also

FUNCTION DFF (D, CLK, CLRN, PRN)
   RETURNS (Q);

COMPONENT DFF
   PORT (d   : IN STD_LOGIC;
      clk : IN STD_LOGIC;
      clrn: IN STD_LOGIC;
      prn : IN STD_LOGIC;
      q   : OUT STD_LOGIC );
END COMPONENT;

Inputs PRN CLRN CLK D	Output Q
L H X X H L X X L L X X H H L H H H H H L X H H H X	H L Illegal L H Qo* Qo

* Qo = level of Q before clock pulse

All flipflops are positive-edge-triggered.

Back to Top