See Also

FUNCTION DFFE (D, CLK, CLRN, PRN, ENA)
   RETURNS (Q);

COMPONENT DFFE
   PORT (d   : IN STD_LOGIC;
      clk : IN STD_LOGIC;
      clrn: IN STD_LOGIC;
      prn : IN STD_LOGIC;
      ena : IN STD_LOGIC;
      q   : OUT STD_LOGIC );
END COMPONENT;

Inputs CLRN PRN ENA D CLK	Output Q
L H X X X H L X X X L L X X X H H L X X H H H L H H H H H H X X L	L H Illegal Qo* L H Qo*

* Qo = level of Q before clock pulse

All flipflops are positive-edge-triggered.

When the ENA (clock enable) input is high, the flipflop passes a signal from D to Q. When the ENA input is low, the state of Q is maintained, regardless of the D input.

For devices that do not support clock enable, logic synthesis generates logic equations representing flipflops with clock enables. These logic equations correctly emulate the logic specified in the project.

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