VHDL

Using Conversion Functions



The std_logic_arith package in the ieee library includes four sets of functions to convert values between SIGNED and UNSIGNED types and the predefined type INTEGER.

Four versions of each function are available; the correct version for each function call is determined through operator overloading.

Two operands are required for the CONV_UNSIGNED, CONV_SIGNED, and CONV_STD_LOGIC_VECTOR functions: the value to be converted and an integer that specifies the size of the converted value. If the value to be converted is smaller than the expected size, the value is extended as necessary.

The Compiler adds zeros to the MSBs for UNSIGNED values and uses sign- extension for SIGNED values. The following example shows an 8-bit adder with UNSIGNED-type inputs and an INTEGER-type output.

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY adder IS
    PORT (op1, op2 : IN UNSIGNED(7 DOWNTO 0);
          result   : OUT INTEGER);
END adder;

ARCHITECTURE maxpld OF adder IS
BEGIN
    result <= CONV_INTEGER(op1 + op2);
END maxpld;

In this example, the ieee library is declared, and the std_logic_1164 and std_logic_arith packages are specified. The inputs are declared with type UNSIGNED, and the output is declared with type INTEGER.

In the architecture, op1 and op2, which are both of type UNSIGNED, are added together, converted to type INTEGER with the CONV_INTEGER conversion function, and assigned to result. If this assignment was made without using the CONV_INTEGER conversion function, the Compiler would generate an error during processing.


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