See Also

Process Statements include a set of sequential statements that assign values to signals. These statements allow you to perform step-by-step computations. Process Statements that describe purely combinatorial behavior can also be used to create combinatorial logic. To ensure that a process is combinatorial, its sensitivity list must contain all signals that are read in the process. A sensitivity list contains the signals that cause the Process Statements to execute if their values change.

You can use Process Statements to create sequential logic. See Implementing Sequential Logic for more information.

The following example shows a Process Statement that counts the number of bits in signal d. Signal d is the only signal contained in the sensitivity list that follows the PROCESS keyword, that is, the only signal to which the process is sensitive.

ENTITY proc IS
   PORT
   (
      d     : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
      q     : OUT INTEGER RANGE 0 TO 3
   );
END proc;

ARCHITECTURE maxpld OF proc IS
BEGIN

   PROCESS (d)   -- count the number of set bits with the value 1 in word d
      VARIABLE num_bits : INTEGER;
   BEGIN
      num_bits := 0;
 
      FOR i IN d'RANGE LOOP
         IF d(i) = '1' THEN
            num_bits := num_bits + 1;
         END IF;
      END LOOP;
  
      q <= num_bits;
   END PROCESS;

END maxpld;

In this example, d is declared as an array in the Entity Declaration. Every time through the FOR loop, i is set to the next value, and d(i) accesses information from the d array. If d(i) equals 1, the If Statement increments num_bits. The num_bits variable is then assigned to the signal q, which is also declared in the Entity Declaration.

For more information, see the following sections of the IEEE Std 1076-1993 IEEE Standard VHDL Language Reference Manual:

• Section 8.6: If Statement
• Section 8.8: Loop Statement
• Section 9.2: Process Statement

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