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Quartus® II software version 2.1 does not recognize Verilog HDL state machines. Instead, it synthesizes state machines as generic logic. The Compiler will not report state information, and you cannot control the encoding using Quartus II logic options. A future version of the Quartus II software will recognize Verilog HDL state machines and optimize them to deliver improved performance. |
A state machine is a sequential circuit that advances through a number of states. To
describe a state machine in Quartus II Verilog HDL, you can define the state values
as parameters, use an Always Construct that is sensitive to a posedge or negedge
clock for the state register, and use a combinatorial Always Construct as the next-state
logic.
| For state machines, Verilog HDL parameters define constants that are used throughout the module. However, Verilog HDL parameters can also act as Quartus II parameters: they create Verilog HDL parameterized modules that can be implemented with Module Instantiations and altered with Defparam Statements. For more information on Verilog HDL parameters, go to "Section 3.10: Parameters" of the IEEE Std 1364-1995 IEEE Hardware Description Language Based on the Verilog Hardware Description Language manual. For information on using Quartus II parameterized functions, go to Using Parameterized Functions. |
The Verilog HDL example shown below implements a 2-state state machine.
module statmach (clk, in, reset, out);
input clk, in, reset;
output out;
reg out;
reg state;
parameter S0 = 0, S1 = 1;
always @ (state) begin
case (state)
S0:
out = 0;
S1:
out = 1;
default:
out = 0;
endcase
end
always @ (posedge clk or posedge reset) begin
if (reset)
state = S0;
else
case (state)
S0:
state = S1;
S1:
if (in)
state = S0;
else
state = S1;
endcase
end
endmodule
This state machine includes two Always Constructs, one that is combinatorial, and one
that is activated on every positive edge of the clk or reset control signal (and which
therefore infers a register).
The reg state stores the current state of the state machine. The parameter keyword
defines Verilog HDL parameters for the states S0 and S1.
The Case Statement in the second Always Construct defines the transitions between the
states, i.e., it determines which state to enter on the next rising edge of the clock (clk)
or reset.
For more information, see the following sections of the IEEE Std 1364-1995 IEEE Hardware Description Language Based on the Verilog Hardware Description Language manual:
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