DESCRIPTION: With the complexity of systems and SoC
accelerating, system-level verification is quickly becoming the bulk of
the design effort (many wise sources state that verification has
exceeded 50% of total design effort, and we agree). Janick Bergeron,
our VP of Technical Wisdom, shares some insight into system-level
verification issues with this Online Seminar, originally presented at
the 1998 Mentor Graphics Users Group conference in Portland,
Oregon. The abstract has been included below.
About this Online Seminar: You may attend this online seminar
with or without an audio track. However, if you want to hear the
presenter's narration of the slides, you must have the RealAudio
plug-in installed in your browser. You can download and install a free
copy of the RealAudio player by clicking on the RealAudio icon
above. For more information about RealAudio, check out their
website at www.real.com.
ABSTRACT: The elusive "system-level" verification can no longer be
considered a nice-to-have activity, only to be done as time allows in
the schedule. No design is an island: they have to eventually work
within a system and function with other design components. Today's
market pressures not only require first-pass success on silicon but
first-pass success on the entire system. System-level verification
can follow a well defined process to ensure first-time success.
System-level verification differs from component or block-level
verification in two important aspects: visibility and complexity. The
lack of visibility into major components is what defines the "system"
level: the design is primarily composed of large blocks of functionality
that were engineered elsewhere: chipsets in board designs or IP
blocks in ASICs. Complexity is the by-product of the design: the
combination of possible states of the system grows exponentially
with each additional component.
Characteristics of a proven system-level process are presented. They
include planning, documentation, impact on design, scheduling,
staffing, execution, and management. Issues such as tool
requirements, design methodology, and design culture are also
addressed. Throughout the presentation, examples from real-life
system-level verification accomplishments will be used. |
