------------------------------------------------------------
-- Copyright Mentor Graphic Corporation 1991. 
-- All rights reserved.  
------------------------------------------------------------
--
--  Model Title:  bus unit
--  Date Created: 95/10/20 (THU)
--  Author:       T. Ohstuka ( tootsuka@ss.titech.ac.jp )
--
------------------------------------------------------------
-- Model Description: 
--
-----------------------------------------------------------
--
LIBRARY IEEE,ARITHMETIC ;
LIBRARY work ;

USE IEEE.STD_LOGIC_1164.ALL ;
USE ARITHMETIC.STD_LOGIC_ARITH.ALL ;
USE work.CPU_PACKAGE.ALL ;
USE work.ALL ;

ENTITY ex1 IS
   PORT (
         dsw        : IN       STD_LOGIC_VECTOR(7 DOWNTO 0) ;         -- I/O data that are read.
         asw        : IN       STD_LOGIC_VECTOR(7 DOWNTO 0)           -- I/O data that are read.
         ) ;
END ex1 ;

-- ---------------------------------------------------------
--Copyright Mentor Graphic Corporation 1991.
--All rights reserved.
-- ---------------------------------------------------------
--Arch. Body for entity declared in 
------------------------------------------------------------
--

LIBRARY IEEE,ARITHMETIC ;
LIBRARY work ;

USE IEEE.STD_LOGIC_1164.ALL ;
USE ARITHMETIC.STD_LOGIC_ARITH.ALL ;
USE work.ALL ;

ARCHITECTURE struct1 OF ex1 IS
   COMPONENT bu
   PORT (
         alubu          :  OUT   STD_LOGIC_VECTOR(7 DOWNTO 0) ;      -- the result sended to RU
         iob            :  OUT   STD_LOGIC_VECTOR(7 DOWNTO 0) ;      -- I/O data that is written
         ir             :  OUT   STD_LOGIC_VECTOR(7 DOWNTO 0) ;      -- for the instruction fetch
--         oe             :  IN    STD_LOGIC ;   -- Memory output enable signal from MU
         mwr            :  IN    STD_LOGIC ;   -- ALU output enable signal from CU
         wp             :  IN    STD_LOGIC ;   -- Memory write signal form IOU
         mrd            :  IN    STD_LOGIC ;   -- Memory read signal form CU
         alu            :  IN    STD_LOGIC_VECTOR(7 DOWNTO 0) ;     -- the result sended from ALU
         data           :  INOUT STD_LOGIC_VECTOR(7 DOWNTO 0) BUS ;      -- bidirectional data port
         dsw            :  IN    STD_LOGIC_VECTOR(7 DOWNTO 0) ;     -- I/O data that are read
         adr            :  OUT   STD_LOGIC_VECTOR(7 DOWNTO 0) ;      -- address output for MU
         b              :  OUT   STD_LOGIC_VECTOR(7 DOWNTO 0) ;      -- sended to input port B of the ALU
         active         :  IN    STD_LOGIC    -- active signal
        ) ;
   END COMPONENT ;
   COMPONENT cg
   PORT (
         clk1           :  OUT   STD_LOGIC ;
         clk2           :  OUT   STD_LOGIC
        ) ;
   END COMPONENT ;
   COMPONENT cu_syn
   PORT (
         sp_load           :  OUT   STD_LOGIC ;   -- load signal for SP
         acc_load          :  OUT   STD_LOGIC ;   -- load signal for ACC
         rotate_right      :  OUT   STD_LOGIC ;   -- rotate right signal of ACC
         rotate_left       :  OUT   STD_LOGIC ;   -- rotate left signal of ACC
         shift_right       :  OUT   STD_LOGIC ;   -- shift right signal of ACC
         shift_left        :  OUT   STD_LOGIC ;   -- shift left signal of ACC
         zfc_acc_on        :  OUT   STD_LOGIC ;   -- zero flag condition which ACC is zero or not
         zfc_alu_on        :  OUT   STD_LOGIC ;   -- zero flag condition which ALU result is zero
         mar_load          :  OUT   STD_LOGIC ;   -- load signal for MAR
         add_with_carry    :  OUT   STD_LOGIC ;   -- add with carry signal
         sub_with_borrow   :  OUT   STD_LOGIC ;   -- substract with borrow signal 
         pc_out            :  OUT   STD_LOGIC ;   -- output signal for PC
         sp_out            :  OUT   STD_LOGIC ;   -- output signal for SP
         acc_out           :  OUT   STD_LOGIC ;   -- output signal for ACC
         if_carry          :  OUT   STD_LOGIC ;   -- carry jump condition
         if_zero           :  OUT   STD_LOGIC ;   -- zero jump condition
         pc_load           :  OUT   STD_LOGIC ;   -- load signal for PC
         clk1              :  IN    STD_LOGIC ;   -- phase 1 clock
         clk2              :  IN    STD_LOGIC ;   -- phase 2 clock
         io_write          :  OUT   STD_LOGIC ;   -- I/O write signal
         init              :  IN    STD_LOGIC ;   -- initialize signal
         carry             :  IN    STD_LOGIC ;   -- carry flag
         zero              :  IN    STD_LOGIC ;   -- zero flag
         active            :  OUT   STD_LOGIC ;   -- active signal ( RUN signal )
         mrd               :  OUT   STD_LOGIC ;   -- memory read signal
         mwr               :  OUT   STD_LOGIC ;   -- memory write signal
         ir                :  IN    STD_LOGIC_VECTOR(7 DOWNTO 0) ;      -- instruction resistor
         alu_f_ctl         :  OUT   STD_LOGIC_VECTOR(4 DOWNTO 0) ;   -- ALU function control signal (M,S3,S2,S1,S0)
         c_ctl             :  OUT   STD_LOGIC_VECTOR(2 DOWNTO 0) ;     -- ALU carry control signal (A,B,C)
         stop0             :  OUT   STD_LOGIC ;   -- stop signal
         last_cycle0       :  OUT   STD_LOGIC ;   -- last cycle of the instruction ( ir_clear )
         rff0              :  IN    STD_LOGIC     -- output of run FF
        ) ;
   END COMPONENT ;
   COMPONENT eu
   PORT (
         clk1           :  IN    STD_LOGIC ;   -- input 2 phases clocka
--         clk2           :  IN    STD_LOGIC ;   --  ,,
         a              :  IN    STD_LOGIC_VECTOR(7 DOWNTO 0) ;      -- A port of the ALU input
         b              :  IN    STD_LOGIC_VECTOR(7 DOWNTO 0) ;      -- B port of the ALU input
         c_ctl          :  IN    STD_LOGIC_VECTOR(2 DOWNTO 0) ;  -- CARRY control
         acc_msb        :  IN    STD_LOGIC ;   -- MSB of ACC
         acc_lsb        :  IN    STD_LOGIC ;   -- LSB of ACC
         add_with_carry    :  IN    STD_LOGIC ;   -- add with carry control
         sub_with_borrow   :  IN    STD_LOGIC ;   -- substract with borrow control
         alu_f_ctl         :  IN    STD_LOGIC_VECTOR(4 DOWNTO 0) ;  -- ALU functinality control
         zfc_acc_on        :  IN    STD_LOGIC ;   -- ZERO flag control for ACC value
         zfc_alu_on        :  IN    STD_LOGIC ;   -- ZERO flag control for ALU value
         zfc_acc        :  IN    STD_LOGIC ;      -- ZERO flag control for the result of shift/rotate in ACC
         alu            :  OUT   STD_LOGIC_VECTOR(7 DOWNTO 0) ;         -- the result of ALU
         carry          :  OUT   STD_LOGIC ;      -- CARRY flag
         zero           :  OUT   STD_LOGIC        -- ZERO flag
        ) ;
   END COMPONENT ;
   COMPONENT iou
   PORT (
         clk1           :  IN    STD_LOGIC ;
         clk2           :  IN    STD_LOGIC ;
         io_write       :  IN    STD_LOGIC ;
         start          :  OUT   STD_LOGIC ;
         halt           :  OUT   STD_LOGIC ;
         init           :  OUT   STD_LOGIC ;
         wp             :  OUT   STD_LOGIC
        ) ;
   END COMPONENT ;
   COMPONENT mu
   PORT (
         clk1           :  IN    STD_LOGIC ;
         clk2           :  IN    STD_LOGIC ;
         adr            :  IN    STD_LOGIC_VECTOR(7 DOWNTO 0) ;
         asw            :  IN    STD_LOGIC_VECTOR(7 DOWNTO 0) ;
         mrd            :  IN    STD_LOGIC ;
         mwr            :  IN    STD_LOGIC ;
         wp             :  IN    STD_LOGIC ;
         active            :  IN    STD_LOGIC ;
         mar_load       :  IN    STD_LOGIC ;
--         oe             :  OUT   STD_LOGIC ;
         data           :  INOUT  STD_LOGIC_VECTOR(7 DOWNTO 0) BUS ;
         mar_ref        :  OUT   STD_LOGIC_VECTOR(7 DOWNTO 0) ;
         init           :  IN    STD_LOGIC 
        ) ;
   END COMPONENT ;
   COMPONENT rf
   PORT (
          clk1          :  IN    STD_LOGIC ; -- phase I clock
          init          :  IN    STD_LOGIC ; -- init 
          start         :  IN    STD_LOGIC ; -- start
          halt          :  IN    STD_LOGIC ; -- halt
          last_cycle    :  IN    STD_LOGIC ; -- last cycle of the instruction
          stop          :  IN    STD_LOGIC ; -- stop
          rff           :  OUT   STD_LOGIC   -- output of run FF
        ) ;
   END COMPONENT ;
   COMPONENT ru
   PORT (
         clk1           :  IN    STD_LOGIC ;
         init           :  IN    STD_LOGIC ;
         alubu          :  IN    STD_LOGIC_VECTOR(7 DOWNTO 0) ;
         carry          :  IN    STD_LOGIC ;
         zero           :  IN    STD_LOGIC ;
         pc_out            :  IN    STD_LOGIC ;
         sp_out            :  IN    STD_LOGIC ;
         acc_out        :  IN    STD_LOGIC ;
         pc_load        :  IN    STD_LOGIC ;
         sp_load        :  IN    STD_LOGIC ;
         acc_load       :  IN    STD_LOGIC ;
         if_carry       :  IN    STD_LOGIC ;
         if_zero        :  IN    STD_LOGIC ;
         rotate_right      :  IN    STD_LOGIC ;
         rotate_left    :  IN    STD_LOGIC ;
         shift_right    :  IN    STD_LOGIC ;
         shift_left        :  IN    STD_LOGIC ;
         a              :  OUT   STD_LOGIC_VECTOR(7 DOWNTO 0) ;
         acc_msb        :  OUT   STD_LOGIC ;
         acc_lsb        :  OUT   STD_LOGIC ;
         zfc_acc        :  OUT   STD_LOGIC ;
         acc_ref        :  OUT   STD_LOGIC_VECTOR(7 DOWNTO 0) ;
         pc_ref         :  OUT   STD_LOGIC_VECTOR(7 DOWNTO 0) ;
         sp_ref         :  OUT   STD_LOGIC_VECTOR(7 DOWNTO 0)
        ) ;
   END COMPONENT ;
   SIGNAL  alubu,iob,ir,alu,adr,b,a,acc_ref,pc_ref,sp_ref,mar_ref
                                            : STD_LOGIC_VECTOR(7 DOWNTO 0) ;
   SIGNAL  data                             : STD_LOGIC_VECTOR(7 DOWNTO 0) ;
   SIGNAL  alu_f_ctl
                                            : STD_LOGIC_VECTOR(4 DOWNTO 0) ;
   SIGNAL  c_ctl
                                            : STD_LOGIC_VECTOR(2 DOWNTO 0) ;
   SIGNAL  mwr,wp,mrd ,clk1,clk2,sp_load,acc_load,rotate_right,rotate_left,
           shift_right,shift_left,zfc_acc_on,zfc_alu_on,halt,start,mar_load,
           add_with_carry,sub_with_borrow,pc_out,sp_out,acc_out,if_carry,if_zero,
           pc_load,io_write,init,carry,zero,active,acc_msb,acc_lsb,zfc_acc,
           stop,last_cycle,rff
                                            : STD_LOGIC ;
BEGIN
   f1 : bu
      PORT MAP (alubu,iob,ir,mwr,wp,mrd,alu,data,dsw,adr,b,active) ;
   f2 : cg
      PORT MAP (clk1,clk2) ;
   f3 : cu_syn
      PORT MAP (sp_load,acc_load,rotate_right,rotate_left,shift_right,
         shift_left,zfc_acc_on,zfc_alu_on,mar_load,add_with_carry,
         sub_with_borrow,pc_out,sp_out,acc_out,if_carry,if_zero,pc_load,
         clk1,clk2,io_write,init,carry,zero,active,mrd,mwr,ir,alu_f_ctl,
         c_ctl,stop,last_cycle,rff) ;
   f4 : eu
      PORT MAP (clk1,a,b,c_ctl,acc_msb,acc_lsb,add_with_carry,
         sub_with_borrow,alu_f_ctl,zfc_acc_on,zfc_alu_on,zfc_acc,alu,
         carry,zero) ;
   f5 : iou
      PORT MAP (clk1,clk2,io_write,start,halt,init,wp) ;
   f6 : mu
      PORT MAP (clk1,clk2,adr,asw,mrd,mwr,wp,active,mar_load,data,mar_ref,init) ;
   f7 : ru
      PORT MAP (clk1,init,alubu,carry,zero,pc_out,sp_out,acc_out,
         pc_load,sp_load,acc_load,if_carry,if_zero,rotate_right,rotate_left,
         shift_right,shift_left,a,acc_msb,acc_lsb,zfc_acc,
         acc_ref,pc_ref,sp_ref) ;
   f8 : rf
      PORT MAP (clk1,init,start,halt,last_cycle,stop,rff) ;
END struct1 ;