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-- Copyright Mentor Graphic Corporation 1991. 
-- All rights reserved.  
------------------------------------------------------------
--
--  Model Title:  memory unit
--  Date Created: 95/10/29 (Sun)
--  Author:       T. Ohtsuka
--
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-- Model Description: 
--
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--
LIBRARY IEEE,ARITHMETIC ;
USE IEEE.STD_LOGIC_1164.ALL ;
USE ARITHMETIC.STD_LOGIC_ARITH.ALL ;

LIBRARY work ;
USE work.cpu_package.ALL ;
USE work.ALL ;

ENTITY mu IS
   PORT (
         clk1             :  IN     STD_LOGIC ;
         clk2             :  IN     STD_LOGIC ;
         adr              :  IN     STD_LOGIC_VECTOR(7 DOWNTO 0) ;
         asw              :  IN     STD_LOGIC_VECTOR(7 DOWNTO 0) ;
         mrd              :  IN     STD_LOGIC ;
         mwr              :  IN     STD_LOGIC ;
         wp               :  IN     STD_LOGIC ;
         active           :  IN     STD_LOGIC ;
         mar_load         :  IN     STD_LOGIC ;
--         oe               :  OUT    STD_LOGIC ;
         data             :  INOUT  STD_LOGIC_VECTOR(7 DOWNTO 0) BUS ;
         mar_ref          :  OUT    STD_LOGIC_VECTOR(7 DOWNTO 0) ;
         init             :  IN     STD_LOGIC
        ) ;
END mu ;

-- ---------------------------------------------------------
--Copyright Mentor Graphic Corporation 1991.
--All rights reserved.
-- ---------------------------------------------------------
--Arch. Body for entity declared in 
------------------------------------------------------------
--
 
LIBRARY IEEE ;
LIBRARY work ;

USE IEEE.STD_LOGIC_1164.ALL ;
USE IEEE.STD_LOGIC_1164_EXTENSIONS.ALL ;
USE work.cpu_package.ALL ;
USE work.ALL ;

ARCHITECTURE behav1 OF mu IS

CONSTANT   mssize   : Integer := 256 ;
TYPE       Msfile IS ARRAY( NATURAL RANGE <>) OF STD_LOGIC_VECTOR(7 DOWNTO 0) ;

SIGNAL     address  : STD_LOGIC_VECTOR(7 DOWNTO 0) ;
SIGNAL     oe0 : STD_LOGIC ;  -- output enable for RAM
SIGNAL     we0 : STD_LOGIC ;  -- write enable for RAM
SIGNAL     data0 : STD_LOGIC_VECTOR(7 DOWNTO 0) ;
SIGNAL     mar : STD_LOGIC_VECTOR(7 DOWNTO 0) ;                           -- memory address resistor
SIGNAL     ow_ctl : STD_LOGIC_VECTOR(1 DOWNTO 0) ;

BEGIN

oe0 <= ( mrd OR ((NOT active) AND (NOT wp))) ;
we0 <= ( mwr OR ((NOT active) AND wp)) ;
mar_ref <= mar ;
-- oe <= oe0 ;

WITH active SELECT
  address <= mar        WHEN '1',
             asw        WHEN '0',
             "XXXXXXXX" WHEN OTHERS ;

mar_process : PROCESS(clk1)
 BEGIN
   IF P_rising(clk1) THEN
      IF mar_load = '1' THEN 
         mar <= adr ; 
      END IF ;
    END IF ;
 END PROCESS ;

ram_process : PROCESS(init,oe0,clk1)
 VARIABLE  ms : Msfile(mssize - 1 DOWNTO 0) ;  -- memory strage
 BEGIN
  IF P_falling(init) THEN
--  IF Sw_rising(init) THEN
-- test program initialization --
     ms(16#00#) := "11011000" ;   -- LOAD ACC from Memory
     ms(16#01#) := "00010010" ;   -- adr.16#12#
     ms(16#02#) := "01000010" ;   -- setsp  set SP register
     ms(16#03#) := "11111111" ;   -- data 16#FF#
     ms(16#04#) := "01000000" ;   -- call   call subroutine
     ms(16#05#) := "00100000" ;   -- adr.16#20#
     ms(16#06#) := "00110000" ;   -- jp     jump
     ms(16#07#) := "00000000" ;   -- adr.16#00#
     ms(16#12#) := "00000001" ;   -- data
     ms(16#20#) := "00010001" ;   -- inc    increment ACC
     ms(16#21#) := "01000001" ;   -- rtn    return
     ms(16#FF#) := "00000000" ;   -- data
     ms(16#10#) := "10000010" ;   -- data
     ms(16#11#) := "00000001" ;   -- data
------------------
  END IF ;
  CASE oe0 IS
    when '1' => data <= ms(Mar_int(address)) ;
    when '0' => data <= Z ;
    when OTHERS => NULL ;
  END CASE ;
  IF P_rising(clk1) THEN
     IF we0 = '1' THEN
        ms(Mar_int(address)) := data ;
     END IF ;
   END IF ;
  END PROCESS ;

END behav1 ;