SYN_PARA.VHD VHDL Code for Parwan CPU by Zainalabedin Navabi



 
--	Model Name	: syn_para.vhd 

--	Author		: Zainalabedin Navabi 

--	Last Updated	: 09 / 15 / 1996

--	This document is © copyrighted by the Author.

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
--
PACKAGE synthesis_parameters IS
CONSTANT single_byte_instructions : std_logic_vector (3 DOWNTO 0) := "1110";
CONSTANT cla : std_logic_vector (3 DOWNTO 0) := "0001";
CONSTANT cma : std_logic_vector (3 DOWNTO 0) := "0010";
CONSTANT cmc : std_logic_vector (3 DOWNTO 0) := "0100";
CONSTANT asl : std_logic_vector (3 DOWNTO 0) := "1000";
CONSTANT asr : std_logic_vector (3 DOWNTO 0) := "1001";
CONSTANT jsr : std_logic_vector (2 DOWNTO 0) := "110";
CONSTANT bra : std_logic_vector (3 DOWNTO 0) := "1111";
CONSTANT indirect : std_logic := '1';
CONSTANT jmp : std_logic_vector (2 DOWNTO 0) := "100";
CONSTANT sta : std_logic_vector (2 DOWNTO 0) := "101";
CONSTANT lda : std_logic_vector (2 DOWNTO 0) := "000";
CONSTANT ann : std_logic_vector (2 DOWNTO 0) := "001";
CONSTANT add : std_logic_vector (2 DOWNTO 0) := "010";
CONSTANT sbb : std_logic_vector (2 DOWNTO 0) := "011";
CONSTANT jsr_or_bra : std_logic_vector (1 DOWNTO 0) := "11";
--
CONSTANT zero_12 : std_logic_vector (11 DOWNTO 0) := "000000000000";
CONSTANT zero_8 : std_logic_vector (7 DOWNTO 0) := "00000000";
END synthesis_parameters;