Contents

• 1 Project Goals
• 2 Design Considerations
• 3 Software Design
  • 3.1 Interrupt Handler
  • 3.2 FPGA Configuration and Diagnostic Software
    • 3.2.1 Bit-file download program
    • 3.2.2 Generic Bullwinkle Console
  • 3.3 Recording Control Software
• 4 Hardware Design
  • 4.1 Experimental Address Counter Card
    • 4.1.1 Detection of Valid Memory References
    • 4.1.2 PC Timer-Tick Interrupt
    • 4.1.3 Results
  • 4.2 Rocky: Interface Subsystem Design
  • 4.3 Bullwinkle: Recording Subsystem Design
  • 4.4 Boris and Natasha: Buffer Module Design
  • 4.5 Bullwinkle Interface Specification
• 5 Construction and Testing
  • 5.1 Construction of Rocky
  • 5.2 Construction of Bullwinkle
  • 5.3 Parts List
• 6 Conclusion
  • 6.1 Final Status Report
  • 6.2 Assessment of Goals
  • 6.3 General Purpose Benefits
• References
• A Software Tools
• B Tutorial: Using ABEL for GALs
  • B.1 ABEL to GAL Makefile
• C Tutorial: Using VHDL for FPGAs
  • C.1 VHDL to FPGA Makefile
  • C.2 vhdl-vl.h
  • C.3 vhdl-syn.h
  • C.4 boris.dcsh
• D C Source Code
  • D.1 busmon.c
  • D.2 staller.c
  • D.3 download.c
  • D.4 console.c
  • D.5 string.c
  • D.6 capture.c
  • D.7 lfsr.c
• E ABEL Source Code
  • E.1 busmon.abl
  • E.2 isyspld.abl
  • E.3 addrcomp.abl
  • E.4 iodecode.abl
  • E.5 bstate.abl
  • E.6 btrigger.abl
• F VHDL Source Code
  • F.1 boris.v
  • F.2 natasha.v
  • F.3 pointers.v
• G Other Files
  • G.1 boris.cst
  • G.2 natasha.cst
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