FPGAs are an efficient hardware target when only small series are needed, or for rapid prototyping. The FPGAs are complex enough to implement more than glue logic, including complex designs up to several thousands gates. As the logic capacity of FPGAs increases, synthesis for FPGAs is becoming more important.
To efficiently exploit increased logic capacity of FPGAs, synthesis tools and efficient synthesis methods for FPGAs targeting become necessary. One solution to designing large designs efficiently is to use VHDL [IEE88] synthesis. Several synthesis tools exist for mapping these descriptions to various FPGA families.
Using a synthesis-based approach, retargeting a design to other technologies becomes possible at little extra cost. Thus, synthesis is attractive for designing chips with small series and for rapid prototyping. When using FPGAs for rapid prototyping, synthesis can be targeted at FPGAs to exercise it for verification purposes, and later an ASIC implementation can be derived.
By using synthesis tools, the modeling, verification and implementation processes can be integrated. The major advantage of synthesis-based designs is that the same hardware description language code can be used for verification and implementation. This integrated design flow reduces the amount of code that has to be maintained and the risk of inconsistencies between different models.
Once the functional correctness of the model has been proved, the same code should be usable to generate a hardware implementation. Ideally, this process would require only recompilation with a silicon compiler to yield the final chip. In reality, synthesis is a much longer process: the circuit description has to be evolved to a form suitable for synthesis (certain constructs are illegal for synthesis, etc.). This process is a gradual one, where components can be replaced one by one, verifying that the resulting implementation is correct.
While ideally, the synthesizable VHDL model should be the same for all target technologies, the efficiency of the resulting design is very much dependent on the description and technology used. This paper discusses optimization issues and methodology for VHDL designs targeted at FPGAs. While this issue has been raised for ASIC designs [Sel94], many issues remain for FPGA targets.
Due to their architecture, optimization problems found in ASIC designs may be amalgamated, heightened or outright reversed for FPGA designs. In this respect, especially LUT-based architectures (such as the Xilinx devices used as example in this paper) are different due to their coarse-grained architecture, while finer/grained architectures behave more like ASICs.
Designing with FPGAs, one of the major differences is that logic functions of the same size cannot be traded: there is a given number of every resource, and whether it is used or not will not change chip size. On the other hand, trading a `cheaper' (less complex) cell for a more `expensive' (more complex) one can actually improve the device budget, if there is an ample amount of the more expensive resource available.
We discuss design strategies for generating efficient VHDL models for FPGA synthesis. These results were collected during several projects [Mau95], [Wal95], [Jau94], [SW94], [SWG94]. The results presented here were obtained empirically by generating various descriptions for the same semantic operation, compiling them and comparing their timing and area characteristics.
This paper is organized as follows: in section 2, we describe the environment used to collect the data. Section 3 shows the usage of usage of fast-carry logic, and section 4 gives an overview of finite state machine optimization for FPGAs. Optimization of multiplexing structures is covered in section 5, and section 6 discusses storage structures. Section 7 describes the interaction between synthesis tools and target specific fitters for placement and routing, and we draw our conclusions in section 8.