To become familiar with standard cell place/route methodology via the 'AutoCells' tool.
'bj_struct.S' - the netlist file defining the design. This is the blackjack player example which was discussed in the ASIC design (CAD) course. It contains 103 standard cells.
'AutoCells.PAR' - a parameter file for AutoCells. The parameters defined in this file control the place/route operations within AutoCells. You will be modifying parameters inside of this file.
'lib.L' - an L file which defines all of the cells used within our design. It is needed to serve as the library reference for the cells referenced within 'bj_struct.S'.
'batch.cmd' - a batch command file for running AutoCells.
'build_lib.COM' - a command file used by the 'build_lib' tool which builds routing models of our cells which is then used by the router within AutoCells. More on this later.
2. We will first create a layout in the 'scn12hp' technology.
aa. Make sure the following environment variable is defined in your .cshrc file:
setenv MSU_SCMOS /mpl/projects/cddd/cell_libs/scmos/a. The first step we need to do is create a router file equivalent of our 'bj_struct.S' netlist for use by AutoCells. Change into the 'scn12hp' directory and start up Led with the command:
Led -t scn12hp -l /ecad/local/tech/rel/gdt/ -load /mpl/projects/cddd/cell_libs/scmos/mentor/schematics/menu.gThe 'menu.g' include file defines the Led symbols for the cells referenced within 'bj_struct.S'. From the 'Files' menu within Led, execute the 'Read L File' command and read in the 'bj_struct.S' file. You will see that all of the symbols will be placed on top of one another because the 'bj_struct.S' file is just a netlist file - it does not contain any schematic placement information. In fact, this file was converted from a Viewlogic netlist via the EDIF import mechanism (it is nice to know you can get designs done in Viewlogic over into Mentor via this route..). Then, from the 'Files' menu, execute the 'Write Router File' command and write out the router file as 'bj_struct.R'. This will be the design input file for AutoCells. You can now close Led. This step only has to be done ONCE - repeat this step only if the netlist file changes.
b. A routing model for all cells referenced by our netlist file must be built so that the router in AutoCells can operate properly. AutoCells uses a 'full-obstruction' routing model which means that it will route through a cell in a particular layer if it finds no obstructions for the route. In order to do this, each cell must be analyzed to determine the obstructions for each routing layer. To build this routing model, execute:
build_lib -t scn12hp -l /ecad/local/tech/rel/gdt/ lib.LThis will create a new file called 'cell_models.L' which has the routing model for each cell referenced in the 'lib.L' file. The command file 'build_lib.COM' drives this process. In this file for the 'scn12hp' process, we define the MET1, MET2, and VIA layers as the obstruction layers since we are going to be routing with MET1 and MET2. This step only has to be done ONCE - it would only have to be repeated if the layout for an individual cell changed.
c. Before running AutoCells, lets discuss the details of its operation. AutoCells can run in either interactive mode or batch mode. DO NOT RUN AUTOCELLS until you have read ALL OF THE FOLLOWING TEXT. You should be familiar with both modes. To run AutoCells in batch mode do:
AutoCells -B -c batch.cmdThe 'batch.cmd' file instructs AutoCells to do the following steps:
'Create' - create the initial database and read in the parameters from the AutoCells.PAR. All files created by AutoCells will be in the 'AutoCells.DB' sub-directory except for the final layout which will be placed in the current directory (in 'bj_struct.L').
'Place' - do initial placement of the cells into rows.
'Improve' - try to improve the placement
'Connect' - do the global routing
'Route' - do detailed channel routing and compaction (if compaction is turned on).
'Flatten' - flatten the design into one .L file (in this case, 'bj_struct.L').
AutoCells operations are logged to 'AutoCells.DB/*.trace' and 'AutoCells.DB/channel*/*.trace' files. You can run AutoCells in interactive mode via:
AutoCellsThis will bring up the AutoCells window which has a text window for logging messages. To run each of the individual steps, put the cursor over the background and use the right mouse button to bring up the AutoCells menu. Select 'Execute Function' and then select the function (Create, Place, Improve, etc) you wish to execute. You can graphically view the results of any step by selecting the 'View Results' function from the main menu and then choosing the function along with the 'pic' choice (selecting 'stats' which just print out the statistics generated by that function).
The AutoCells.PAR file is extremely important as it defines parameters which controls every aspect of the various functions within AutoCells. There are too many parameters to discuss all of them in detail - we will experiment with only a couple of the parameters in this lab. What follows is a short explanation of some of the parameters - comments in the 'AutoCells.PAR' file can also used to determine the functions of the parameters:
'netlist' - defines the input netlist file name.
'cells' - L file which defines reference library
'outfile' - output filename for resulting layout
'tech_dir' - technology directory
'tech' - technology name
'hor1' - first horizontal routing layer. For scn12hp, this is MET1.
For scn08hp, this is MET3.
'ver1' - first vertical routing layer. This is MET2 for
both scn12hp, scn08hp.
'h1v1' - connecter between 'hor1' and 'ver1' routing layers
(M1M2 for scn12hp, M2M3 for scn08hp).
'full_obstruction_mode' - when set to '1', use obstruction model for routing. This
we will use for this lab.
'compact' - when '1', do compaction of layout after detailed
routing is finished (when '0', no compaction).
'compact_no_jogs' - when '0', allow compactor to insert horizontal jogs into routes (when '1', no horizontal jogs).
'slack' - This parameter is typically set as "set slack '(30)" where
30 is the percentage of white space inserted in each row for
routing. This line is usually commented out in the parameter file,
if you are having problems with the channel router failing, try
uncommenting this line and experiment with different slack values.
d. Layout creation . Create three layouts - one with no compaction,
one with compaction but no horizontal jogs in routes, one with compaction with
horizontal jogs allowed. Record the size of each layout
(found in Autocells.DB/tile.trace) and comment in your lab report on differences
you can observe in the layouts.
After creating a layout, you will do notch/gap filling on your layout.
Assuming the final layout is in 'bj_struct.L',
do:
/mpl/projects/cddd/tools/bin/notch_fill_sc.pl lib.L bj_struct.LThis will do notch and gap filling on your layout. Notches/gaps can form in various layers due to the layout/compaction process used by Autocells; these will produce false design rule errors. This script will automatically fill these notches/gaps. After doing this, run 'mcDrGdt' to perform a DRC on the final 'bj_struct.L'. You WILL get some design rule errors relating to MOSIS rule 8.5; these can be ignored (they will be listed as Rules 67, 68, 69, and 70). These errors are already present in the other cells referenced within 'bj_struct.L'. There should be no other errors in the layout.
e. For the minimum size layout created in step 2d, run the 'x_seg' program as follows:
x_seg -t scn12hp -l /ecad/local/tech/rel/gdt -inc lib.L -o bjstruct.seglen bj_struct.LThe 'x_seg' program extracts the routing segments used in each net. This information can be used to compute the Resistance/Capacitance values for each net. The extracted information is placed in the file 'bj_struct.seglen'. Using the information in this file, compute the RC time constant on the CLK_TERM net. To get the values MET2_Substrate capacitance, MET3_Substrate capacitance, MET2/MET3 sheet resistance, and VIA/VIA2 contact resistances, look in the files:
/ecad/local/tech/build/mosis_r7/scn*/base/mosis.prmFor the scn12hp technology, assume one gate load is 30fF. A clock gate load is a 'CLK2' terminal on a D flip-flop cell (dfrf301).
3. Create one layout in the scn08hp technology. For the layout, enable compaction with horizontal jogs allowed in routes. Repeat step 2e for this layout and compute the RC value for the CLK_TERM net. For the scn08hp technology, assume one gate load is 18fF. Before creating the layout, you must create the 'bj_struct.R' file and the cell routing models as described in step 2.
4. Compare the best layout area achieved for the scn12hp process with that of the scn08hp process. CONVERT both layouts from 'mm' dimensions to lambda dimensions and compute the area reduction due to over-the-cell routing allowed by use of MET3 in the scn08hp process. Recall that lambda=0.6 um for the scn12hp process, and lambda=0.4 um for the scn08hp process.