32x32 Register File Example

Register files are generally fast RAMS with multiple read and write ports. In Memory Builder,to build a register file you need to specify two parameters for the size of the register file, word (the number of the words) and bpw(bits per word). The assembled register file layout has following terminals.

1. Global terminals: vdd and gnd
   
   
2. Address for read and write
   • Addr_r: bus address for reading
   • Addr_w: bus address for writing
   
   
3. Control Signals
   • G_raddr:     gate-in control for read address(high valid)
   • G_waddr:    gate-in control for write address(high valid)
   • G_din_b:    gate-in control for din(low valid)
   • WE_b:      write enable (low valid)
   
   
4. IO signals:
   • Din:   input data bus
   • Dout:   output data bus

The register file can have three kinds of operations:

• Write data to specified address.
• Read data from specified address.
• Write-through on specified address.

Final Results

• Layout of the 32x32 register file generated from Memory Builder.
  
  
• Lsim simulation result for the 32x32 register file .

VHDL model for 32x32 register file

Before you use this model, you need to download utilities & IEEE packages from MPL VHDL Model Collection . This model has been tested successful on Mentor Quick VHDL. You can compile the downloaded VHDL model and simulate.

Click to download the VHDL model.

Any comments and problems? Please feel free to send mail to reese@erc.msstate.edu.