Microsystems Prototyping Laboratory

aof2301: 2 / 3 AND / OR MUX

• Gate Level Schematic
• Transistor Level Schematic
• Layout
• Logic Equation
• Inputs
• Outputs
• Truth Table
• Terminal Location and Capacitance
• Characterization Data

here.

-------------------------------------------------
A	B	C	D	E	F	O
-------------------------------------------------
1	1	1	x	x	x	1
x	x	x	1	1	1	1
0	x	x	0	x	x	0
0	x	x	x	0	x	0
0	x	x	x	x	0	0
x	0	x	0	x	x	0
x	0	x	x	0	x	0
x	0	x	x	x	0	0
x	x	0	0	x	x	0
x	x	0	x	0	x	0
x	x	0	x	x	0	0
-------------------------------------------------

--------------------------------------------
Name	X_loc	Y_loc	   Capacitance (fF)
	lambda  lambda   2U	1.2U	0.8U
--------------------------------------------
A1	8.4	22	59.6	27.6	18.6
B1	16	30	53.3	24.8	17.9
C1	32	30	52.7	25.0	17.1
D2	81	37	61.0	28.2	18.6
E2	92	30	53.3	24.8	17.9
F2	104	35	52.1	24.7	17.1
O	60.05	31.3	-	-	-
--------------------------------------------

• Delay Information