Microsystems Prototyping Laboratory

aoif2201: 2 / 2 AND / NOR MUX

• Gate Level Schematic
• Transistor Level Schematic
• Layout
• Logic Equation
• Inputs
• Outputs
• Truth Table
• Terminal Location and Capacitance
• Characterization Data

here.

---------------------------------
A	B	C	D	O
---------------------------------
1	1	x	x	0
x	x	1	1	0
0	x	0	x	1
0	x	x	0	1
x	0	0	x	1
x	0	x	0	1
---------------------------------

--------------------------------------------
Name	X_loc	Y_loc	   Capacitance (fF)
	lambda  lambda   2U	1.2U	0.8U
--------------------------------------------
A1	42	22	67.4	31.7	20.7
B1	31	31	62.0	29.8	19.3
C2	21	31	60.8	29.6	19.1
D2	4	23.5	66.0	31.4	20.5
O	11.5	32	-	-	-
--------------------------------------------

• Delay Information