Microsystems Prototyping Laboratory

blf00201: 3 / 2 OR / AND MUX

• Gate Level Schematic
• Transistor Level Schematic
• Layout
• Logic Equation
• Inputs
• Outputs
• Truth Table
• Terminal Location and Capacitance
• Characterization Data

here.

---------------------------------
A	B	C	D	O
---------------------------------
0	0	x	x	0
x	x	0	x	0
x	x	x	0	0
1	x	1	1	1
x	1	1	1	1
---------------------------------

--------------------------------------------
Name	X_loc	Y_loc	   Capacitance (fF)
	lambda  lambda   2U	1.2U	0.8U
--------------------------------------------
A1	28	34	59.6	28.9	24.4
B1	57.5	23	64.0	30.2	25.1
C2	16	31	64.2	30.6	26.1
D2	9	27.5	74.2	34.8	28.8
O	70	29	-	-	-
--------------------------------------------

• Delay Information