Microsystems Prototyping Laboratory

dfnf311: D-FF W / Q & Q_b

Gate Level Schematic of the standard cell "dfnf311".

Schematic of the standard cell "dfnf311" with device sizes in lambda.

Layout of the standard cell "dfnf311"

here.

Logic Equation: Q = (Qn-1 * CLK2) + (DATAn-1 * CLK2')

Q_b = Qn'

Input(s): CLK2, DATA1

Output(s): Q, Q_b

Truth Table 

-----------------------------
CLK	D	Q	Q_b
-----------------------------
h2l	x	DATA1	DATA1'
l2h	x	Qn-1	Qn-1'
-----------------------------

Terminal Location and Capacitance Table 

--------------------------------------------
Name	X_loc	Y_loc	   Capacitance (fF)
	lambda  lambda   2U	1.2U	0.8U
--------------------------------------------
CLK2	12.5	35	66.3	30.7	20.1
DATA1	49.5	45	49.0	23.3	14.5
Q	199	20	-	-	-
Q_b	166	34.5	-	-	-
--------------------------------------------

Characterization Data