Microsystems Prototyping Laboratory

faf001: FULL ADDER

• Gate Level Schematic
• Transistor Level Schematic
• Layout
• Logic Equation
• Inputs
• Outputs
• Truth Table
• Terminal Location and Capacitance
• Characterization Data

here.

-----------------------------------------
A1	B1	CIN2	SUM	CO
-----------------------------------------
0	0	0	0	0
0	0	1	1	0
0	1	0	1	0
0	1	1	0	1
1	0	0	1	0
1	0	1	0	1
1	1	0	0	1
1	1	1	1	1
-----------------------------------------

--------------------------------------------
Name	X_loc	Y_loc	   Capacitance (fF)
	lambda  lambda   2U	1.2U	0.8U
--------------------------------------------
A1	13	30.5	68.5	34.2	28.7
B1	75	35	56.9	28.0	25.3
CIN2	258	27	69.5	34.8	29.3
CO	234.5	28	-	-	-
SUM	167	31.5	-	-	-
--------------------------------------------

• Delay Information