Microsystems Prototyping Laboratory

invf121: TRI-STATE INVERTER

• Gate Level Schematic
• Transistor Level Schematic
• Layout
• Logic Equation
• Inputs
• Outputs
• Truth Table
• Terminal Location and Capacitance
• Characterization Data

here.

--------------------
ENb	A1	O
--------------------
0	0	1
0	1	0
1	X	Z
--------------------

--------------------------------------------
Name	X_loc	Y_loc	   Capacitance (fF)
	lambda  lambda   2U	1.2U	0.8U
--------------------------------------------
A1	12	27	73.3	36.3	23.6
ENb	94	32	73.0	36.2	23.6
O	53	31.5	-	-	-
--------------------------------------------

• Delay Information