Microsystems Prototyping Laboratory

invf181: ENABLED INVERTER W / SET

• Gate Level Schematic
• Transistor Level Schematic
• Layout
• Logic Equation
• Inputs
• Outputs
• Truth Table
• Terminal Location and Capacitance
• Characterization Data

here.

----------------------------------
EN2	DATA1	SET4	O
----------------------------------
x	x	0	1
0	x	1	z
1	DATA1	1	DATA1'
----------------------------------

--------------------------------------------
Name	X_loc	Y_loc	   Capacitance (fF)
	lambda  lambda   2U	1.2U	0.8U
--------------------------------------------
DATA1	28	29	64.7	31.2	26.0
EN2	39	23	79.3	38.0	31.7
O	16.5	33	-	-	-
SET4	7	35	59.5	28.0	23.1
--------------------------------------------

• Delay Information