Microsystems Prototyping Laboratory

lhrf311: D-LATCH W / RST & ACTIVE HIGH CLOCK

• Gate Level Schematic
• Transistor Level Schematic
• Layout
• Logic Equation
• Inputs
• Outputs
• Truth Table
• Terminal Location and Capacitance
• Characterization Data

here.

Q-b = Qn'

------------------------------------------
CLK	DATA	RST	Q	Q_b
------------------------------------------
0	x	1	Qn-1	Q_bn-1
1	0	1	0	1
1	1	1	1	0
x	x	0	0	1
------------------------------------------

--------------------------------------------
Name	X_loc	Y_loc	   Capacitance (fF)
	lambda  lambda   2U	1.2U	0.8U
--------------------------------------------
CLK2	20	28	71.9	55.9	35.2
DATA1	12	28	72.7	58.2	39.6
Q	141	28	-	-	-
Q_b	162	20	-	-	-
RST3	89	23	71.0	52.6	38.1
--------------------------------------------

• Delay Information
• Hold Time Information
• Setup Time Information