Microsystems Prototyping Laboratory

nanf201: 2 INPUT NAND

• Gate Level Schematic
• Transistor Level Schematic
• Layout
• Logic Equation
• Inputs
• Outputs
• Truth Table
• Terminal Location and Capacitance
• Characterization Data

here.

-----------------
A	B	O
-----------------
0	0	1
0	1	1
1	0	1
1	1	0
-----------------

--------------------------------------------
Name	X_loc	Y_loc	   Capacitance (fF)
	lambda  lambda   2U	1.2U	0.8U
--------------------------------------------
A1	10	23	66.5	31.1	20.4
B1	19	23	59.7	28.5	18.5
O	27	13	-	-	-
--------------------------------------------

• Delay Information