Microsystems Prototyping Laboratory

nanf211: 2 INPUT NAND / AND

• Gate Level Schematic
• Transistor Level Schematic
• Layout
• Logic Equation
• Inputs
• Outputs
• Truth Table
• Terminal Location and Capacitance
• Characterization Data

here.

O2 = A1 * B1

---------------------------
A	B	O1	O2
---------------------------
o	x	1	0
x	0	1	0
1	1	0	1
---------------------------

--------------------------------------------
Name	X_loc	Y_loc	   Capacitance (fF)
	lambda  lambda   2U	1.2U	0.8U
--------------------------------------------
A1	9.5	23	70.9	34.2	22.5
B1	19	24	63.4	31.4	20.6
O1	32	18	-	-	-
O2	41	16	-	-	-
--------------------------------------------

• Delay Information