Microsystems Prototyping Laboratory

nanf251: A' NAND B

• Gate Level Schematic
• Transistor Level Schematic
• Layout
• Logic Equation
• Inputs
• Outputs
• Truth Table
• Terminal Location and Capacitance
• Characterization Data

here.

-----------------
A	B	O
-----------------
0	0	1
0	1	0
1	0	1
1	1	1
-----------------

--------------------------------------------
Name	X_loc	Y_loc	   Capacitance (fF)
	lambda  lambda   2U	1.2U	0.8U
--------------------------------------------
A1	10.5	24	45.5	21.5	13.6
B2	31	24	60.2	29.2	19.0
O	39	13.5	-	-	-
--------------------------------------------

• Delay Information