Cell puuf000: PULL UP

Microsystems Prototyping Laboratory

puuf000: PULL UP

Gate Level Schematic
Transistor Level Schematic
Layout
Logic Equation
Inputs
Outputs
Truth Table
Terminal Location and Capacitance
Characterization Data

Gate Level Schematic of the standard cell "puuf000".

Schematic of the standard cell "puuf000" with device sizes in lambda.

Layout of the standard cell "puuf000"

here.

Logic Equation: O = 1

Input(s):

Output(s): out

Truth Table

Terminal Location and Capacitance Table

--------------------------------------------
Name	X_loc	Y_loc	   Capacitance (fF)
	lambda  lambda   2U	1.2U	0.8U
--------------------------------------------
out	16	12	-	-	-
--------------------------------------------

Characterization Data

Delay Information