This short tutorial discusses use of the Logic Synthesis service implemented via Synopsys. This service can synthesize VHDL/EDIF/Verilog files to MSU SCMOS/GCMOS standard cell libraries. It can also translate a netlist in one library to another library. The service is setup to only synthesize to MSU standard cell libraries.
Much of the power of the Synopsys synthesis environment is NOT exposed via this GUI; the intended use of this GUI is for routine, quick synthesis experiments.
You will need the following input file(s) for this tutorial:
The main window for the Synopsys synthesis service is shown
below:
The various fields in the service window must be filled in before a job can be submitted to the server. The fields are explained below.
Left clicking on the Input File button will pop up a file dialog box thru which you can specify your input file. Alternatively, you can use the typein field to specify the pathname to your file. The service supports VHDL, EDIF, and Verilog input files. The file suffix does NOT indicate what type of input file this is.
Use this choice menu to specify what input file type (VHDL, EDIF, Verilog) is being submitted.
This choice menu is only needed if your input file is a netlist of cells from one of the supported library choices. This needs to be specified if you are translating a netlist from one library to another. If your input file is a behavioral specification then this parameter is ignored.
Use this typein field to specify the name of the TOP-LEVEL design entity in your input file. If the design file is VHDL and only contains one entity/architecture pair, then the design name should match the entity name (NOT the file name!). If there is more than one entity/architecture in the input file, then it should match the name of the TOP-LEVEL entity.
Use this choice menu to specify what output file type (VHDL, EDIF, Verilog) you want back.
Use this choice menu to to specify the output library for the synthesis operation.
This choice-menu controls whether or not the design hierarchy should be flattened before synthesis. This option only needs to be considered if there is more than one design element (in VHDL, more than one entity/architecture pair) in the input file.
The default for this choice menu is 'Compile'. The only time the 'Translate' option is needed is if the input file is a gate netlist, and you want to preserve the gate structure as much as possible when converting to another library.
This typein field allows a user to specify a netname that should not be affected by the 'compile' operation (i.e., a clock buffer network that should not be changed).
This type-in field contains an integer that specifies a maximum fanout constraint for any input ports or nets for the design. The synthesis tool will attempt to limit the fanout to this value. The units are library dependent; for the MSU cell libraries the units are in femo-farads (fF). The default value of -1 means that this constraint will not be used during synthesis.
This type-in field contains an integer that specifies a maximum area constraint for the resulting design. The synthesis tool will attempt to limit the area to this value. The units are library dependent; for the MSU SCMOS cell libraries the units are in 'lambda'; for the GCMOS cell libraries the units are in microns. The default value of negative means that a this constraint will not be used (if neither an area or speed constraint is specified, then Synopsys will use minimum area as a constraint).
This type-in field contains an integer that specifies a maximum delay constraint to all outputs for the resulting design. The synthesis tool will attempt to limit the delay to this value. The units are library dependent; for the MSU SCMOS cell libraries the units are in nanoseconds.
Left clicking on this button will pop up a dialog box thru which you can specify output directory. Alternatively, you can use the typein field to specify the pathname to your directory. The directory will be created if it does not exist; files which already exist in the directory will be overwritten upon completion of the job.
During job execution a status window will appear which will allow you to monitor the progress of the job execution. At this point there is no way for the user to interact with the job during execution (we want to add at least a 'kill' button in the near future).
When the job is complete, the directory specified in the 'output directory' will contain the results files of the synthesis run. A README file in this directory explains what each result file contains.
Run the Synopsys synthesis service using the 'dec3to8.vhd' file referenced above as the input file. The other choices should be:
These options will cause the synthesis tool to use a minimum area constraint during synthesis. Once the above choices have been set, click on the 'Run' button. You should see a log window appear which shows the progression of the Synopsys synthesis file. When the job is finished, you can look in the 'results' directory for the result file which will be called 'dec3to8.edif'. If specify a VHDL output type, then you will get a VHDL structural model back which references gates from the SCMOS library (scn08hp technology).
It is important to realize that you input file is transferred to the server before synthesis, and all result files are transferred back to your local output directory. If you are using a dialup link and are using large input/output files, then this transfer may take a long time.