package Traffic_Package is

 type Color is (Green, Yellow, Red, Unknown);

type State is (
	Highway_Light_Green,
	Highway_Light_Yellow,
	Highway_Light_Green,
	Highway_Light_Yellow);
end Traffic_Package ;


use work.traffic_package.all;
entity traffic_light_controller  is
  generic (
	Long_Time : Time;  -- Minimum green light duration
	Short_Time : Time  --  yellow light duration
	  ) ;
  port (
	Car_On_Farmroad : in Boolean;
	Highway_Light : out Color;
	Farmroad_Light : out Color
       ) ;
end traffic_light_controller;



architecture specification of traffic_light_controller is

	signal Present_State : State := Highway_Light_Green;
	signal Timed_Out_Long : Boolean := FALSE ;
	signal Start_Timer : Boolean := FALSE ;
	
	begin -- specification
	      --process statement which implements the state machine
	Controller_Process:
	process
	begin
	  case Present_State is

		when Highway_Light_Green =>
		    if Car_On_Farmroad and Timed_Out_Long then
			 Start_Timer <= not Start_Timer;
			 Present_State <= Highway_Light_Yellow;
		    end if ;
	

		when Highway_Light_Yellow =>
		    if Timed_Out_Short then
			 Start_Timer <= not Start_Timer;
			 Present_State <= Farmroad_Light_Green;
		    end if ;


		when Farmroad_Light_Green =>
		    if not Car_On_Farmroad or Timed_Out_Long then
			 Start_Timer <= not Start_Timer;
			 Present_State <= Farmroad_Light_Yellow;
		    end if ;

		when Farmroad_Light_Yellow =>
		    if Timed_Out_Short then
			 Start_Timer <= not Start_Timer;
			 Present_State <= Highway_Light_Green;
		    end if ;
	end case;
	wait on
	  Car_On_Farmroad, Timed_Out_Long, Timed_Out_Short;
	end process;


   -- Conditional signal assignment to set highway light

	Highway_Light_Set:
	 with Present_State select 
	   Highway_Light <=
		Green when Highway_Light_Green,
		Yellow when Highway_Light_Yellow,
		Red when
                  Farmroad_Light_Green | Farmroad_Light_Yellow;

   -- Conditional signal assignment to set farm road light

	Farmroad_Light_Set:
	  with Present_State select
		Farmroad_Light <=
		  Green when Farmroad_Light_Green,
		  Yellow when Farmroad_Light_Yellow,
		  Red when
			Highway_Light_Green | Highway_Light_Yellow;

-- process statement to implement timing mechanism

	Timer_Process:
	process
	begin
	  Timed_Out_Long <= FALSE, TRUE after Long_Time;
	  Timed_Out_Short <= FALSE, TRUE after Short_Time;
	wait on Start_Timer;
	end process;

end specification;

architecture Behavior_2 of TL_Controller is
  signal Controler_State : State      := Highway_Light_Green;
  signal               Y : State_Bits := B"00";
 begin
   Y <= State_To_Bits(Controller_State);
 
   process
     variable SumOfProducts : Bit_Vector(0 to 6);
   begin
     Controller_State <= Bits_To_State(Y);
     if  C = '0' and Y(0) = '0' and Y(1) = '0' then
           SumOfProducts := B"0000010" ;
     elsif TL = '0' and Y(0) = '0' and Y(1) = '0' then
           SumOfProducts := B"0000010" ;
     elsif C = '1' and TL = '1' and Y(0) = '0' and Y(1) = '0' then
           SumOfProducts := B"0110010" ;
     elsif TS = '0' and Y(0) = '0' and Y(1) = '1' then
           SumOfProducts := B"0100110" ;
     elsif TS = '1' and Y(0) = '0' and Y(1) = '1' then
           SumOfProducts := B"1110110" ;
     elsif C = '1' and TL = '0' and Y(0) = '1' and Y(1) = '1' then
           SumOfProducts := B"1101000" ;
     elsif C = '0' and Y(0) = '1' and Y(1) = '1' then
           SumOfProducts := B"1011000" ;
     elsif TL = '1' and Y(0) = '1' and Y(1) = '1' then
           SumOfProducts := B"1011000" ;
     elsif TS = '0' and Y(0) = '1' and Y(1) = '0' then
           SumOfProducts := B"1001001" ;
     elsif TS = '1' and Y(0) = '1' and Y(1) = '0' then
           SumOfProducts := B"0011001" ;
     end if;

    Controller_State <= transport
            Bits_to_State(State_Bits(SumOfProducts(0 to 1)));
    ST <= transport SumOfProducts(2);
    HL <= transport Color_Bits(SumOfProducts(3 to 4));
    FL <= transport Color_Bits(SumOfProducts(5 to 6));
    wait on C, TL, TS, Y(0), Y(1);
    end process;
  end Behavior_2;
architecture Behavior1 of PLA is
   type PLA_Matrix is array
    ( Integer range 0 to 9, Integer range 0 to 6 ) of Bit ;
   constant PLA_Outputs : PLA_Matrix := (
     ('0','0','0','0','0','1','0'),
     ('0','0','0','0','0','1','0'),
     ('0','1','1','0','0','1','0'),
     ('0','1','0','0','1','1','0'),
     ('1','1','1','0','1','1','0'),
     ('1','1','0','1','0','0','0'),
     ('1','0','1','1','0','0','0'),
     ('1','0','1','1','0','0','0'),
     ('1','0','0','1','0','0','1'),
     ('0','0','1','1','0','0','1') );

   begin

	process
	 variable New_State: Integer;
        begin
         if In0='0' and In3='0' and In4='0' then
              NewState := 0;
         elsif In1='0' and In3='0' and In4='0' then
              NewState := 1;
         elsif In0='1' and In1='1' and In3='0' and In4='0' then
              NewState := 2;
         elsif In2='0' and In3='0' and In4='1' then
              NewState := 3;
         elsif In2='1' and In3='0' and In4='1' then
              NewState := 4;
         elsif In0='1' and In1 = '0' and In3='1' and In4='1' then
              NewState := 5;
         elsif In0='0' and In1='0' and In3='1' and In4='1' then
              NewState := 6;
         elsif In1='1' and In3='1' and In4='1' then
              NewState := 7;
         elsif In2='0' and In3='1' and In4='0' then
              NewState := 8;
         elsif In2='1' and In3='1' and In4='1' then
              NewState := 9;
         else
           assert (FALSE) report "Error in PLA" severity Error;
         end if;

        Out0 <= PLA_Outputs(New_State,0);
        Out1 <= PLA_Outputs(New_State,1);
        Out2 <= PLA_Outputs(New_State,2);
        Out3 <= PLA_Outputs(New_State,3);
        Out4 <= PLA_Outputs(New_State,4);
        Out5 <= PLA_Outputs(New_State,5);
        Out6 <= PLA_Outputs(New_State,6);

       wait on In0, In1, In2, In3, In4;
     end process;

  end Behavior1;