 ..... Guidelines and Coding
Styles
These guidelines and coding styles relate to VHDL
code development. For limitations and restrictions
on using this material see the DISCLAIMER page.
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VHDL Quick Reference Card
by Qualis Design Corporation
Verilog Quick Reference Card
by Qualis Design Corporation
IEEE Standard 1164 Quick Reference Card
by Qualis Design Corporation
VHDL Taxonomy Document 
by RASSP Taxonomy Working Group
VHDL Performance Model Interoperability
Guidelines
Version: 2.0, February , 1996
by : Honeywell Technology Center
VHDL SIMULATIONS - TIPS FOR SPEEDING
by V.K. Madisetti
Guidelines for Writing VHDL Models in a Team
Environment
Bell-Northern Research Ltd. Report
by Janick Bergeron
Style Guidelines for Effective Use of Parallel and
Multithreaded VHDL Simulators
by Dr. John Willis and Dr. William Paulsen
A Taxonomy of Parallel VHDL Simulation
Techniques
by Gregory Peterson and John Willis
VHDL Model Guidelines
by European Space Agency (ESA)
VHDL Models for Board Level Simulation
Recommendations for development and usage of
VHDL models for Board-Level Simulation by
European Space Agency (ESA)
The Usage of VHDL in the European Space
Agency
by European Space Agency (ESA)
The VHDL Standard : An Overview of Activities,
Organizations and European Tool Efforts
by European Space Agency (ESA)
A VHDL Modeling Guide
Alternate site for document
by US Navy Standard Hardware and Reliability
Program (SHARP) Technology Independent
Representation of Electronic Products (TIREP)
report
- UNIX file format (name: vhdlmdlgde.2.0.tar.Z, size:
1,439,420 Bytes)
- DOS file format (name: vhdlmg20.zip, size: 884,671 Bytes)
VHDL-Verilog Interoperability Guide
Cadence Design Systems, Inc.
by Victor Berman
Tricks and Techniques for Writing VITAL 3.0
Compliant ECL Models
by the Free Model Foundation
Board-level Component Modeling Using VITAL
by Russell E. Vreeland, TRW Ground Systems
Center
Integrating FMF Models with Concept Libraries
by Richard Munden, Acuson Corporation
Connecting the System to the Chip:
Using VHDL/VITAL for Board-level Simulation
by Russell E. Vreeland, Free Model Foundation
Style Guide for VHDL Simulation Models Written
for the FMF Library Data Base
by Richard Munden, munden@acuson.com
Raymond Steele, rsteele@emu.sp.trw.com
Russell Vreeland, russv@ikos.com
Free Model Foundation
Copyright © 1994-98 RASSP E&F
All rights reserved.
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