Your VHDL Problems Answered

In this section, we answer general VHDL and synthesis problems sent to us, or we cover discussion topics which arise from our training courses.

Getting Initializations to Work Properly
The Subtleties of Attributes
Drivers on Signals
Using Aliases as a Coding Shortcut
Matching Don't Care's ('-') in Expressions
Converting Between Types
Simulation of VHDL
Integer Types and Subtypes
Writing Synthesisable Register Descriptions

If you have a general VHDL modeling or synthesis problem that you would like answered and included in these pages, please e-mail us with your query.

Doulos Training Courses
VHDL FAQ

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This page was last updated 24^th July 1996.

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