Synthesizing Verilog

How do you write good synthesisable Verilog code to give you the hardware you want?

Synthesis is a broad term often used to describe very different tools. Synthesis can include silicon compilers and function generators used by ASIC vendors to produce regular RAM and ROM type structures. Synthesis in the context of this tutorial refers to generating random logic structures from Verilog descriptions. This is best suited to gate arrays and programmable devices such FPGAs.

Synthesis is not a panacea! It is vital to tackle High Level Design using Verilog with realistic expectations of synthesis.

The definition of Verilog for simulation is cast in stone and enshrined in the Language Reference Manual. Other tools which use Verilog, such as synthesis, will make their own interpretation of the Verilog language.

It is not sufficient that the Verilog is functionally correct; it must be written in such a way that it directs the synthesis tool to generate good hardware, and moreover, the Verilog must be matched to the idiosyncrasies of the particular synthesis tool being used. We shall tackle some of these idiosyncracies during these Verilog tutorials.

There are currently three kinds of synthesis:

behavioural synthesis
high-level synthesis
RTL synthesis

There is some overlap between these three synthesis domains. We will concentrate on RTL synthesis. The essence of RTL code is that operations in the Verilog are tied to particular clock cycles. The synthesised netlist exhibits the same clock-by-clock cycle behaviour, allowing the RTL testbench to be easily re-used for gate-level simulation.

We will look at examples of writing Verilog code for synthesis at a later stage.

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