VHDL Quick Reference

For the sake of brevity, throughout the following examples, names are used without being declared.

Syntax Reference
Expressions, Operators and Names
Reserved Identifiers
The STANDARD Package
The TEXTIO Package
The std_logic_1164 Package

Syntax Reference

package Pack is
  type Enum is (Unknown, '0', '1');
  type Int is range 0 to 255;
  type float is range 0.0 to 1.0;
  type Byte is array (7 downto 0) of Bit;
  type Mem is array (Integer range <>) of Int;
  type Intx is record
    Value: Integer;
    Defined : Boolean;
  end record;
  constant C1 : Int := 255;
  constant CV2 : Mem (0 to 511) := (1, 2, 3, others => 4);
  procedure P (Const : T; Var: out T; signal Sig : inout T);
  function "+" (L, R: T) return T;
end Pack;

package body Pack is
  procedure P (Const : T; Var: out T; signal Sig : inout T);
    -- declarations
  begin
    -- sequence of statements
  end P;

  function "+" (L, R: T) return T is
    -- declarations
  begin
    -- sequence of statements
    return Expr;
  end "+";
end Pack

library Lib;
use Lib.Pack.all;

entity Ent is
  generic (G : Time := 0 ns);
  port ( P1 in T;
  P2 : out T := '0';
  P3, P4 : inout T);
end Ent;

-- Behavioural description
architecture A 1 of Ent is
  signal Sig1, Sig2: Typ := Init;
begin
  Proc: process (Ck, D)
    -- declarations
  begin
    -- sequence of statements
  end process Proc;

  process
    variable Var : Typ := Init;
  begin
    wait until Rising_edge (Ck);
    wait for 10 ns;
    wait;
    Sig <= Expr after Delay;
    Sig <= Expr1 after D1, Expr2 after D2, Expr3 after D3;
    Var := Expr;
    case C is 
      when C1 =>
        -- sequence of statements
      when C2 | C3 | C4 to C8 =>
        -- sequence of statements
      when other =>
        null;
    end case;
    if Reset then
      -- sequence of statements
    elsif Ck'Event and Ck = '1' then
      -- sequence of statements
    else
      -- sequence of statements
    end if;
    for i in 1 to N loop
      -- sequence of statements
      exit
      -- sequence of statements
    end loop;
    while C loop
      -- sequence of statements
    end loop;
    assert D'stable (10 ns)
      report "Setup error"
      severity warning;
      report "End of simulation"
  end process;

  L1 : Sig1 <= A + B after 100 ns;
  L2 : Sig2 <= A * B after 1 us;
end A1;

architecture A2 of Ent is
  component Comp
    generic (G: Time := 0 ns);
    port (A, B: in T := '0';
    F : out T);
  end component;
  signal S1, S2, S3: Typ := Init;
begin
  L0 entity Lib.Ent2(Arch)
    port map (S1, S2, S3);
  L1: Comp port map (S1, S2, S3);
  L2: Comp generic map (G => 5 ns)
           port map (S1, S2, S3);
end A2;

configuration Cfg1 of Ent is
  for A1
  end for;
end Cfg1;

library Lib;
use Lib.all;
configuration Cfg2 of Ent is
  for A2
    for all: Comp
      use configuration Lib.Cfg3;
    end for;
  end for;
end Cfg2;

Expressions, Operators and Names

() TypeName()
** abs not
* / mode rem
+ - &
sll srl sla sra rol ror
= /= < <= > >=
and nand or nor xor xnor
123 1_2_3 1e6 2#1110# 16#FF#
"0101" O"77" X"FF"
ABC def Ghi A123 A_B_C
Name(Expr)
Name(Expr1 to Expr2)
T'Low T'High T'Image
A'Range A'Reverse_Range
S'Event S'Stable(T) S'Delayed(T)
E'Path_Name

Reserved Identifiers

abs           exit          not           signal  
access        file          null          shared  
after         for           of            sla     
alias         function      on            sll  
all           generate      open          sra  
and           generic       or            srl  
architecture  group         others        subtype 
array         guarded       out           then  
assert        if            package       to  
attribute     impure        port          transport     
begin]        in            postponed     type   
block         inertial      procedure     unaffected        
body          inout         process       units  
buffer        is            pure          until  
bus           label         range         use  
case          library       record        variable   
component     linkage       register      wait          
configuration literal       reject        when            
constant      loop          rem           while  
disconnect    map           report        with     
downto        mod           return        xnor  
else          nand          rol           xor  
elsif         new           ror             
end           next          select          
entity        nor           severity

The STANDARD Package

package Standard is -- (Library Std)
  type Boolean is (False, True); 
  type Bit is ('0', '1'); 
  type Character is (NUL, SOH, STX, ..., 
    ' ', '!', '"', '#', '$', '%', '&', ''', 
    '(', ')', '*', '+', ',', '-', '.', '/', 
    '0', ..., '9', ':', ';', '<', '=', '>',  '?', 
    '@', 'A', ..., 'Z', '[', '\', ']', '^', '_', 
    '`', 'a', ..., 'z', '{', '|', '}', '~', DEL); 
  
  type Severity_level is (Note, Warning, Error, Failure); 
  type Integer is range implementation_defined; 
  type Real is range implementation_defined; 
  type Time is range implementation_defined 
    units 
      fs;
      ps = 1000 fs;
      ns = 1000 ps;
      us = 1000 ns; 
      ms = 1000 us; 
      sec = 1000 ms; 
      min = 60 sec; 
      hr = 60 min; 
    end units; 
  function Now return Time; 
  subtype Natural is Integer range 0 to Integer'high; 
  subtype Positive is Integer range 1 to Integer'high; 
  type String is array (Positive range ) of Character; 
  type Bit_vector is array (Natural range ) of Bit; 
end Standard;

The TEXTIO Package

package textio is -- (library std)
  type line is access string;     type text is file of string;
  type side is (right, left);     subtype width is natural;

  file input : text is in "std_input";
  file output : text is out "std_output";

  -- in read and write below, type t is one of... bit, bit_vector,
  -- boolean, character, integer, real, string, time

  procedure readline(file f: text; l: out line);
  procedure read(l:inout line; value: out t);
  procedure read(l:inout line; value: out t; good : out boolean);
  procedure writeline(f : out text; l : inout line);
  procedure write(l : inout line; value : in t;
    justified: in side := right; field: in width := 0
    digits: in natural := 0
    unit: in time := ns);
  -- function endfile(f : in text) return boolean;
end textio;

The std_logic_1164 Package

package Std_logic_1164 IS -- (Library IEEE)

  type Std_ulogic is ( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-');
  type Std_ulogic_vector is array ( natural range  ) of std_ulogic;
  function Resolved ( s : std_ulogic_vector ) return std_ulogic;
  subtype std_logic IS resolved std_ulogic;
  type std_logic_vector is array ( natural range ) OF std_logic;
  subtype X01 is resolved std_ulogic range 'X' TO '1';  
  -- also subtypes X01Z, UX01, and UX01Z
  
  function "and"  ( l : std_ulogic; r : std_ulogic ) return UX01;
  -- also "nand" "or" "nor" "xor" "xnor" "not" 
  -- also defined on std_ulogic_vector and std_logic_vector

  function To_* (S: *) return *;
  -- from bit bitvector StdULogic StdLogicVector std_ulogic_vector
  -- to bit bitvector StdULogic StdLogicVector std_ulogic_vector X01 X01Z UX01

  function rising_edge  (signal s : std_ulogic) return boolean;
  function falling_edge (signal s : std_ulogic) return boolean;
end Std_logic_1164;

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