Doulos VHDL Training, Comprehensive VHDL for Systems

Comprehensive VHDL (Systems) focuses on the use of VHDL in the context of hardware design, including ASIC, FPGA and hardware system design, and test bench construction. The course teaches the most effective VHDL coding styles for simulation at the ASIC and system levels.

The course is organised as two modules, Introduction to VHDL (2 days) and Further VHDL (3 days). You may attend these modules at separate times or complete the course in one week. Introduction to VHDL provides a good grounding in VHDL, ideal for engineers evaluating the technology, or looking for cost effective preparation for VHDL based projects. Further VHDL is the ideal preparation for design projects, emphasizing VHDL style for system level modelling and simulation, writing test benches, and project organization. For the fullest project preparation for ASIC design, the course is complemented by the Doulos Advanced VHDL for Synthesis course, covering RTL synthesis for ASIC design.

Over 50% of the course time is devoted to practical workshops using leading simulation tools. A wide range of tools are made available on all public courses. On site courses can be run with tools of the client's choice.

What The Course Will Give You

• A working knowledge of the VHDL language as used for hardware design
• Practical experience in using VHDL simulation tools
• Knowledge of the most effective VHDL coding styles for system level simulation
• An understanding of how VHDL fits into the hardware system design flow
• An understanding of VHDL project organization

Application Topics

• Introduction
• Methodology
• VHDL Style
• Project management
• Making Effective use of VHDL

Introduction to VHDL (Days 1 and 2) gives a good grounding in VHDL, including robust testbench design, ideal for engineers evaluating the technology.

Further VHDL (Days 3, 4 and 5) provides additional essential preparation for system design projects, emphasizing VHDL style for system level modeling, handling large VHDL designs and project organization.

Comprehensive VHDL for FPGA/ASIC
Made-to-measure training

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