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Doulos Verilog Training, Verilog for FPGA/ASIC Design
   
  Verilog for FPGA/ASIC Design is a practical 4 day training course which teaches the Verilog Hardware Description Language and its use in the context of ASIC and FPGA design. The course includes lectures, written exercises, and practical hands-on exercises. The course can be run with any Verilog simulator and any of the leading synthesis tools that have a Verilog capability. Basic instruction in operating both simulation and synthesis tools is also included.

What The Course Will Teach You

  • How Verilog fits into the ASIC/FPGA design flow
  • How to use the Verilog language for hardware design and logic synthesis
  • How to write good Verilog test fixtures to verify your designs
  • How to avoid common mistake with Verilog and synthesis

Course Organization and Target Audience
The 4 day course is organised as two modules which may be attended separately:

Day1: Verilog Primer

An introduction to the Verilog language suitable for engineers and engineering managers with no previous knowledge of Verilog.

Days 2-4: Verilog for Synthesis

Suitable for engineers and engineering managers who have attended Day 1, who have attended another Verilog language course, or who have some previous experience of using the Verilog language but no knowledge or limited knowledge of how to write Verilog for synthesis.

  Syllabus  

Verilog HDL

  • The scope and application of Verilog
  • Verilog in the ASIC/FPGA design flow
  • Levels of abstraction and coding style
  • The Verilog language syntax and semantics in detail: modules, ports, instantiation, hierarchy, wires, registers, parameters, names, numbers, comments, directives, system calls, operators, continuous assignments, always, initial, timing controls, if, case, loop, disable, tasks, functions
  • The Verilog language gate level modelling constructs in brief: primitives, net types, delays, strengths, specify, UDPs
  • The Verilog language high level modelling constructs in brief: named events, wait, fork, external disable, intra assignment timing controls

Synthesis

  • Logic, RTL and datapath synthesis
  • How to write synthesizable Verilog code
  • Controlling the synthesis of combinational logic and registers from Verilog
  • Describing and synthesizing finite state machines and arithmetic structures
  • Advanced RTL Verilog coding style
  • Understanding the limitations of synthesis and optimization, and avoiding pitfalls
  • Using hierarchy and constraints to control synthesis

Simulation

  • Write Verilog test fixtures to describe the simulation environment
  • Reading and writing text files from Verilog
  • An introduction to high level modelling in Verilog
  • Using Verilog for gate level simulation
  
   

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