4.2.3 LPM_AND

 

Copyright © 1998 University of Manchester

Ports
Port Name
Type
Usage
DescriptionComments
Data
I
Required
Data input Vector, LPM_Size times LPM_Width wide
Result
O
Required
Result of AND operators Vector, LPM_Width wide

Properties
Property
Usage
ValueComments
LPM_Width
Required
LPM Value > 0Width of output vector.

Number of AND gates.

LPM_Size
Required
LPM Value > 0Number of inputs to each AND gate.

Number of input buses.

Function

Result0 = Data0X0 & Data1X0 & Data2X0 & … & DataLPM_Size-1X0

Result1 = Data0X1 & Data1X1 & Data2X1 & … & DataLPM_Size-1X1

Result2 = Data0X2 & Data1X2 & Data2X2 & … & DataLPM_Size-1X2

Resulti = Data0Xi & Data1Xi & Data2Xi & … & DataLPM_Size-1Xi

Where i goes from 0 to (LPM_Width - 1).

Example

Suppose the designers have three 8-bit buses and they want to AND the corresponding bits of the three buses. This is done using an LPM_AND with an LPM_Width = 8 and an LPM_Size = 3. The LPM_Width of eight indicates that there are eight AND gates, and the LPM_Size of three indicates that each AND gate has three inputs.

This diagram is for illustrative purposes only and is not intended to specify any implementation details.

The function performed by the LPM_AND gate in this case is:

Out[0] = Result0 = Data0X0 & Data1X0 & Data2X0 = C[0] & B[0] & A[0]

Out[1] = Result1 = Data0X1 & Data1X1 & Data2X1 = C[1] & B[1] & A[1]

Out[2] = Result2 = Data0X2 & Data1X2 & Data2X2 = C[2] & B[2] & A[2]

Out[3] = Result3 = Data0X3 & Data1X3 & Data2X3 = C[3] & B[3] & A[3]

Out[4] = Result4 = Data0X4 & Data1X4 & Data2X4 = C[4] & B[4] & A[4]

Out[5] = Result5 = Data0X5 & Data1X5 & Data2X5 = C[5] & B[5] & A[5]

Out[6] = Result6 = Data0X6 & Data1X6 & Data2X6 = C[6] & B[6] & A[6]

Out[7] = Result7 = Data0X7 & Data1X7 & Data2X7 = C[7] & B[7] & A[7]