Ports

Port Name	Type	Usage	Description	Comments
Data	I	Required	Data input. Treated as unsigned binary number.	Vector, LPM_Width wide
Enable	I	Optional	Enable. All outputs low when not active	Default value is Active (High) if absent.
EQ	O	Required	For i = 0 to LPM_Decodes if (i = Data) Eqi = 1 else Eqi = 0	Vector, LPM_Decodes wide. If Data > = LPM_Decodes then all Eqi are 0
Clock	I	Optional	Clock for pipelined usage	Note 1
Aclr	I	Optional	Asynchronous Clear	Note 2

Note 1: The clock port provides for pipelined operation of the LPM_MUX. If a latency other 0 (default value) is specified, then the clock port must be connected.

Note 2: The pipelined initializes to undefined. The Aclr port may be used at any time to reset the pipeline to all 0's asynchronously to clock.

Properties

Property	Usage	Value	Comments
LPM_Width	Required	LPM Value > 0	Width of input vector
LPM_Decodes	Required	0 < LPM Value < = 2LPM_Width	Number of explicit decodes
LPM_Pipeline	Optional	LPM Value > = 0	Default is 0 - non-pipelined

Functions

Enable	Data vector	Eqi that is 1 (high) all other Eqi = 0 (low)
L	X	NONE
H	0000...000	Eq0
H	0000...001	Eq1
...	...	...
H	0000...101	Eq5
...	...	...
H	Data = LPM_Decodes -1	Eq(LPM_Decodes-1)
H	Data = LPM_Decodes	NONE
H	Data > LPM_Decodes	NONE

Note 1: If Data = i and Eq_i is not connected or does not appear in the symbol then all outputs will be low.