D-Type Latch.

Ports

Port Name	Type	Usage	Description	Comments
Data	I	Optional	Data Input to D-Type Latches	Vector, LPM_Width wide Note 1
Gate	I	Required	Latch enable input High (1) = flow through Low (0) = latch
Q	O	Required	Data output from D-type latches	Vector, LPM_Width wide
Aset	I	Optional	Set latch value to all 1's or to the value of LPM_Avalue, if present.	Note 2, Note 3
Aclr	I	Optional	Clear the latch (set to all 0's)	Note 3
TestEnab	I	Note 4	Test enable input
TestIn	I	Note 4	Serial test data input
TestOut	O	Note 4	Serial test data output	TestOut = QLPM_Width-1

Note 1: If the Data input is not used, then either Aset or Aclr must be used.

Note 2: Aset will set the count to the value of LPM_Avalue, if that value is present. If no LPM_Avalue is specified, then Aset will set the count to all ones.

Note 3: Aset and Aclr affect the output (Q_i ) values before the application of polarity to the ports.

Note 4: Either all of the Test ports must be connected or none of them.

Properties

Property	Usage	Value	Comments
LPM_Width	Required	LPM Value > 0	Width of input and output vectors
LPM_Avalue	Optional	LPM Value	Value loaded by Aset
LPM_Pvalue	Optional	LPM Value	Value loaded at power-on

Functions

Aclr Aset	Gate	TestEnab	Output
H	X	X	Asynchronous value. Note 1
L	L	X	Latch holds current value (latched)
L	H	X	Latch is transparent (flow-through)
L	X	H	Qi is shifted into Qi+1 TestIn is loaded into Q0

Note 1: The asynchronous value is determined by which asynchronous port is high: Aclr or Aset. If both asynchronous ports are high, then the output is UNDEFINED. If the LPM_Avalue property is defined, then the Aset port, when active, will set the count to the value of the LPM_Avalue.