4.4.4 LPM_RAM_DQ

 

Copyright © 1998 University of Manchester

Ports:
Port Name
Type
Usage
DescriptionComments
Data
I
Required
Data input to memory Vector, LPM_Width wide
Address
I
Required
Address of memory location Vector, LPM_WidthAd wide
Q
O
Required
Output of memory Vector, LPM_Width wide
InClock
I
Note 1
Synchronous load of memory
OutClock
I
Note 2
Synchronous Q outputs from memory.
WE
I
Required
Write enable control. Enables write to the memory when high (1). Note 3

Note 1: If the InClock port is used, then the WE port acts as an enable for write operations synchronized to the positive going edge of the signal on the InClock port. If the InClock ports is not used, then the WE port acts as an enable for write operations asynchronously.

Note 2: The addressed memory content to Q response is synchronous when the OutClock port is connected. and asynchronous when it is not connected.

Note 3: If only WE is used, the data on the Address port should not change while WE is active (high, 1). If the data on the Address port changes while WE is high (1), then all memory locations that are addressed are over-written with Data.

Properties
Property
Usage
ValueComments
LPM_Width
Required
LPM Value > 0Width of input and output vectors.
LPM_WidthAd
Required
LPM Value > 0Width of Address Port. Note 1.
LPM_NumWords
Optional
LPM Value > 0Number of words stored in Memory. Note 2.
LPM_InData
Optional
REGISTERED | UNREGISTEREDIndicates if Data port is registered. Default is REGISTERED
LPM_Address_Control
Optional
REGISTERED | UNREGISTERED Indicates if Address and WE ports are registered. Default is REGISTERED
LPM_OutData
Optional
REGISTERED | UNREGISTEREDIndicates if Q port is registered. Default is REGISTERED
LPM_File
Optional
File NameFile for RAM initialization.

Note 1: The LPM_WidthAd should be (but is not required to be) equal to: log2(LPM_NumWords). If LPM_WidthAd is too small, some memory locations will not be addressable. If it is too big, then the addresses that are too high will return UNDEFINED.

Note 2: If LPM_NumWords is not used, then it defaults to 2LPM_WidthAd. In general, this value should be (but is not required to be): 2LPM_WidthAd-1 < LPM_NumWords < = 2LPM_WidthAd.

Functions

Random Access Memory. This module can represent asynchronous memory or memory with synchronous inputs and/or outputs.

Synchronous Memory Operations

Synchronous Write to memory
InClock
WE
Memory Contents
X
L
No change
not rising edge
H
No change (requires positive going clock edge)
rising edge
H
The memory location pointed to by Address is loaded with Data. Controlled by WE.

Synchronous Read from memory
OutClock
Output
not rising edge
No Change
rising edgeThe output register is loaded with the contents of the memory location pointed to by Address. Q outputs the contents of the output register. Note 1

Note 1: WE does not act as a clock enable for the output clock.

Asynchronous Memory Operations

Totally asynchronous memory operations occur when neither InClock nor OutClock is connected.
WE
Memory Contents
L
No change
H
The memory location pointed to by Address is loaded with Data. Controlled by WE.

The output Q is asynchronous and reflects the data in the memory to which Address points.