Efficient Technology Mapping

The primary advantage of LPM is that it allows technology-independent design without sacrificing efficiency. The key to the efficiency of LPM is that it allows the technology mapping to work from a higher level of abstraction. This higher level of abstraction allows the technology vendors to optimize the function's fit by making use of special features within the IC's architecture.

A good example of this advantage can be found by looking at the LPM_COUNT module. The typical code fragment used to specify a loadable, enabable counter within VHDL is shown in Figure 1. This code will be synthesized to gates by most logic synthesis tools. Once the counter is synthesized to gates, it is very difficult to recognize as a counter. The result is that the carry-chains found in many high-density PLDs will not be used to implement the counter. In many cases this can double or triple the number of logic elements required to implement a simple counter.

	PROCESS (clk)
            BEGIN
                IF clk'event and clk = '1' THEN
                    IF load = '1' THEN
                        count <= data;
                	ELSIF enable = '1' THEN
                        count <= count + 1;
                    	END IF;
                END IF;
                q <= count;
           	END PROCESS example;

Figure 1. Sample VHDL code fragment that implements 16- bit loadable, enabled counter.

The LPM_COUNT module, on the other hand, allows the technology mapping tool to recognize that the function can use the carry chain resulting in improved performance and efficiency. Fig. 2 shows how the LPM_COUNT function can be instantiated within the same VHDL source. The LPM version of the counter offers nearly a 3-to-1 advantage in silicon efficiency and 4-to-1 advantage in performance.


        BEGIN
           u1: lpm_counter
               port map(data => data_in, q => results,
               load => load, enable => enable, clk => clk);
	END example;

Figure 2. Instantiating an LPM counter