Analog and Mixed-Signal Extensions to VHDL Through Examples

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Table of Contents

  1. Analog and Mixed-Signal Extensions to VHDL Through Examples
  2. Outline
  3. What is VHDL 1076.1
  4. Why is VHDL 1076.1 needed
  5. VHDL 1076.1 Language Architecture
  6. VHDL 1076.1 Highlights (1)
  7. VHDL 1076.1 Highlights (2)
  8. Outline
  9. Parameterized Diode
  10. Diode 1076.1 Model
  11. Terminal
  12. Nature
  13. Electrical Systems Environment
  14. Quantity
  15. Implicit Quantities (1)
  16. Implicit Quantities (2)
  17. Branch Quantity (1)
  18. Branch Quantity (2)
  19. Terminal Attributes
  20. Simultaneous Statements (1)
  21. Simultaneous Statements (2)
  22. Tolerances (1)
  23. Tolerances (2)
  24. Outline
  25. Diode with Self Heating
  26. Diode with Self Heating 1076.1 Model Environment
  27. Diode with Self Heating 1076.1 Model Entity
  28. Diode with Self Heating 1076.1 Model Architecture
  29. Outline
  30. Weighted Summer
  31. Generic Weighted Summer 1076.1 Model Entity
  32. Generic Weighted Summer 1076.1 Model Architecture Declarations
  33. Generic Weighted Summer 1076.1 Model Architecture Statements
  34. Generic Weighted Summer 1076.1 Model Revisited
  35. Outline
  36. Amplifier
  37. Amplifier 1076.1 Model Entity
  38. Amplifier 1076.1 Model Architecture Declarations
  39. Amplifier 1076.1 Model Architecture Statements (1)
  40. Amplifier 1076.1 Model Architecture Statements (2)
  41. Outline
  42. A/D Converter
  43. A/D Converter 1076.1 Model Entity
  44. A/D Converter 1076.1 Model Architecture (1)
  45. A to D Interaction: QâAbove(E)
  46. A/D Converter 1076.1 Model Architecture (2)
  47. A/D Converter 1076.1 Model Architecture (3)
  48. D/A Converter
  49. D/A Converter 1076.1 Model Entity
  50. D/A Converter 1076.1 Model Architecture
  51. Break Statement
  52. Outline
  53. Bouncing Ball
  54. Outline
  55. Signal-Flow Modeling
  56. Outline
  57. Solvability Checks (1)
  58. Solvability Checks (2)
  59. Outline
  60. Structural Hierarchy
  61. PLL: Component Package
  62. PLL: System Description
  63. Outline
  64. Initial Conditions (1)
  65. Initial Conditions (2)
  66. Outline
  67. Frequency Domain Modeling
  68. Current Source
  69. Second Order Lowpass Filter
  70. Outline
  71. Noise Modeling
  72. Noisy Resistor
  73. Noisy Diode
  74. Outline
  75. VHDL 1076.1 Model Execution
  76. 1076.1 Initialization
  77. 1076.1 Simulation Cycle
  78. Outline
  79. Also in VHDL 1076.1
  80. Outline
  81. Conclusion
  82. VHDL 1076.1 Information