| <> |
type MEM is array (natural range <>) of integer; |
box |
| = |
if rst = '0' then ... |
equality |
| /= |
if clk /='1' then ... |
inequality |
| >= |
while mem(i) >= 10 loop .. |
greater than or equal |
| <= |
assert compteur <= 32 ... |
less than or equal |
| <= |
output <= internal_bus after 10 ns; |
signal assignment |
| := |
reg:= internal_bus; |
variable assignment |
| => |
case .. when "10" => outputs <= "101"; |
"then" |
| => |
funct(input1=>"1011", ..) |
"gets" |
| < |
if mem(i) < 64 then .. |
less than |
| > |
if ram(i) > 8 then .. |
greater than |
| " |
report "my message" |
double quote |
| ' |
sortie'delayed(20 ns) |
single quote or tick |
| . |
cell.header |
dot separator |
| : |
signal sortie : bit; |
data : type separator |
| + |
sum: = a + b; |
addition or positive |
| - |
subtr := a- b; |
subtraction or negative |
| / |
period/2 |
division (quotient) |
| * |
mult= a * b; |
multiplication |
| ** |
expo= 2**10; |
exponentation |
| & |
ten_bits = "1010" & six_bits; |
concatenantion |
| | |
when '1' | 'X' => |
vertical bar , or operator |
| ; |
end component; |
instruction or clause terminator |
| # |
8#567# |
sharp (hash) , literal base |
| ( |
(0 to 63 |
left paranthesis |
| ) |
31 downto 0) |
right paranthesis |
VHDL
delimiters