prepared by P. Bakowski

The essential aim of the simulation is to model and to observe the behavior of a circuit in time. VHDL allows to represent the simulation time in terms of pico-nano-micro seconds (physical type). It also enables to model the concurrency which is a natural functional feature of hardware systems.

Temporal domains

Time may be perceived at different levels of modeling/simulation.

• continuous - propagation delays
• discretized by clock signals
• before-after causal order.

These three levels of time modeling are visualized at the design cube below. The propagation delays characterize physical time induced by the physical phenomena.

The clock related timing is related the architectural or structural aspects of the digital hardware (data-flow, bit_vectors).

The causal order is involved by the algorithmic descriptions (behavioral, abstract values).

Discrete event time model

Once the behaviour of a module have been specified, it is possible to simulate the module by executing its bevioural description. This is done by simulating the passage of time in discrete steps.

At some simulation time, a module input may be stimulated by changing the value on an input port; this is called an event.

The module reacts by running the code of its behavioural description and scheduling new values to be placed on the signals connected to its output ports at some later simulated time. This is called scheduling a transaction on that signal.

If the new value is different from the previous value on the signal, an event occurs, and other modules with input ports connected to the signal may be activated.

The simulation starts with an initialisation phase, and then proceeds by repeating a two- stage simulation cycle .

In the initialisation phase, all signals are given initial values, the simulation time is set to zero, and each module's behaviour program is executed. This usually results in transactions being scheduled on output signals for some later time. In the first stage of a simulation cycle, the simulated time is advanced to the earliest time at which a transaction has been scheduled. All transactions scheduled for that time are executed, and this may cause events to occur on some signals.

In the second stage, all modules which react to events occurring in the first stage have their behaviour program executed. These programs will usually schedule further transactions on their output signals. When all of the behaviour programs have finished executing, the simulation cycle repeats. If there are no more scheduled transactions, the whole simulation is completed.

The purpose of the simulation is to gather information about the changes in system state over time. This can be done by running the simulation under the control of a simulation monitor . The monitor allows signals and other state information to be viewed or stored in a trace file for later analysis. It may also allow interactive stepping of the simulation process, much like an interactive program debugger.

Modeling concurrency

VHDL based simulation handles the concurrency allowing multiple processes to execute in parallel. Processes are activated when an event occurs at the sensitivity list of the process.

The executable section of a process may contain several signal and variable assignments. These assignements are arranged and, in case of variable assignements are executed in a sequential (typographic) order. This sequential execution is also called procedural execution.

The variable assignments:

variable a,s,t: integer;

...

a := s + t;

b := a * r;

Note that the new value of a is calculated immediately and is used in the following assignment.

If we rewrite the above expressions using signal objects, we obtain two independent processes (proc_1, proc_2).

signal a,s,t: integer;

...

b <= a * r; -- second process with sensitivity list of a and r (equivalent to)

a <= s + t; -- first process with sensitivity list of s and t (equivalent to)

If we assume that both s and r change at time t0; then both processes are activated simultanoeusly and the new values of a and b are evaluated concurrently at time t0+delta. delta represents one simulation cycle. It is infinitely small but greater than zero. After the evaluation of all assignments scheduled for the given simulation cycle, next simulation cycle starts after a delta time.

In our example the next value for signal a will be ready after a delta time. This in turn will activate the second process and generate a new value for signal b after a following delta time.

Note that the order of execution of signal assignments is independent of their typographic order. This kind of execution is called non-procedural.

proc_1: process(s,t)

begin

a <= s + t;

end process proc_1;

proc_2: process(a,t)

begin

b <= a * r;

end process proc_2;

The following tables provide the comparison between variable and signal evaluations for a given example.

Now we can consider an example of a simple rs flip-flop. The process below describes the operations of this flip-flop using two signal assignments.

rs_p: process(r,s)

begin

q <= r nand nq;

nq <= s nand q;

end process rs_p;

Question:

Is it possible to describe the function of rs flip-flop using variable assignements ?

Modeling explicit delays

Explicit delays are modeled using two kinds of statement:

• after statement (transport, reject)
• wait statement

after statement provides a means to introduce inertial or trasport delays.

Inertial delay model represents the operation of switching circuits. The pulse duration shorter than the switching time of the circuit is not transmitted. Inertial delay rejects the pulses less or equal to the RC time constant.

Transport delay is characteristic of transmission lines that exhibit infinite frequency response: any pulse is transmitted, no matter how short it is.

The following waveforms show two examples demonstrating the operational meaning of both kinds of delays.

Chaining delays in processes

Several consecutive signal assignments may produce different effects depending on the value of signal and type of delays used in the process.

When inertial signal assignment is made, all driver values in the queue past the current time are deleted. This is not the case of transport delays which conserves the previously (in time) assigned values.

More precise rule is given in the table below:

Examples:

reject statement

reject statement has been introduced in VHDL'93. It allows to calibrate precisely the RC time constant value used to reject short impulses.

The reject region is the time interval from between the current time and current time less the rejct time expression (negative time zone is ignored)

sig <= reject 12 ns inertial 10 after 5 ns, 2 after 10 ns, 5 after 15 ns, 9 after 60 ns;

sig <= reject 5 ns inertial 4 after 18 ns, 2 after 30 ns, 5 after 50 ns;

gives:

5 ns : 10

10 ns: 2

15 ns: 2, value 5 is rejected (18-15 < 5)

18 ns: 4

30 ns: 2 (30-18 >5 )

50 ns: 5

60 ns: 5, value 9 is rejected (60-50 < 12)

wait statement (see also)

wait statement provides a powerful mechanism for synchronization of processes.

process

begin

...

wait;-- stops the execution of process, the process waits forever

end process;

There are 3 basic versions of wait statement:

• wait statement with sensitivity list

wait on a,b,c;

a,b,c form sensitivity list; an event on any of it resumes the process execution

• wait statement with logic condition

wait until clk='1';

clk='1' represents the logic condition which must be verified to resume the process execution

• wait statement with timeout condition

constant time_out:time:= 100 ns;

...

wait for time_out;

Note that the same wait condition may be expressed in a differenet manner:

wait on clk until clk='1'; -- wait statement explicitely sensitive to clk

wait until clk='1'; -- wait statement implicitely sensitive to clk

or

wait until clk'event and clk='1'; -- the rising edge is explicitely defined

wait until clk='1'; -- -- the rising edge is implicitely defined

Several combinations of wait versions are allowed:

wait on data, clk until clk='1';

wait on a,b for 50 ns;

wait until input="10101" for 45 ns;

wait for a,b,c until clk='0' for 35 ns;

Processes with multiple wait statements

VHDL processes may be modeled with several wait statements. Such models care used to represent and simulate finite state machines. However, the processes with multiple wait statements are not synthetizable.

Exercice:

The following example shows a simple generator of waveforms. Give the simulation results of this process.

gen_wave: process

begin

s <= 25 after 50 ns;

wait for 25 ns;

s <= 50;

wait for 250 ns;

s <= 250 after 25 ns;

wait for 50 ns;

s <= 500 after 50 ns;

s <= 800 after 100 ns;

wait for 5 ns;

s <= 800;

wait;

end process gen_wave;