prepared by P. Bakowski
This page describes the sequential statements of the VHDL language.
The sequential statements are used to describe the sequences of operations.
The VHDL sequential statements include well-known programming structures
like if .. else conditional statements, switches and loops.
Assignment, If statement, Case
statement, Loop statement, Next
statement, Null statement, Assertions,
VHDL provides a number of constructs used to modify the state
of objects such as variables. These modifications are the results of variable
assignments. The activation of the assignments is decided by control instructions
such as if, case
and loop. In principle,
the variable assignments are (or not) executed in a sequential order following
the order of writing (typo logical order). This order may be modified by
A variable is given a new value using an assignment statement called
in VHDL sequential assignment. In the assignment expression the target
object and the assigned value must have the same base type.
Note that in case when the assignment target is an aggregate,
the value of the expression must be a composite value of the same type
as the target aggregate.
The majority of traditional control instructions used in programming
language is present in VHDL. All of these constructs use conditional expressions
providing boolean result ('true' or 'false')
The simplest control instruction is the if
.. then .. end if statement. It may be completed
keywords to allow multiple conditions. More complex constructs such as
case - end case or loop - end loop permit to describe multiple tests and
statement is used to select one or none of a collection of
statements depending on some condition expression Note that conditions
are expressions resulting in boolean values. If the condition is
evaluated to true,
the corresponding statement list is executed. Otherwise, if the else
clause is present, the else
statement list is executed.
statement must end with a corresponding end
Multiple conditions can be built with if statement followed by elsif
The case statement is used
to select a collection of statements based on the range of values of a
given expression called selection expression.
The selection must be of discrete type or a one-dimensional
array. For the matching choice the expression is selected and the statement
list executed. All the choices must be distinct and all values
must be represented in the choice lists. If some choice is not specified
than the default choice must be indicated through the use of others
statement may be used to explicitly show that no action is required for
a given choice.
In many cases a collection of statements need to executed repeatedly/iteratively
for a specific number of steps until some exit or end condition occurs.
VHDL provides iterative control in the form of loop statements.
A basic loop statement is:
iteration scheme allows a test condition to be evaluated before
each iteration. The iteration proceeds if the test evaluates to true
( test for continuation), otherwise the loop statement terminates.
The for loop is used to
control the exit from the loop based on iterating through some number of
values in a given range. This scheme allows a specified number of
iterations. The counter object (e.g. i ) does
not need to be declared as variable but it does not exist outside the loop.
VHDL provides two additional statements ( next
and exit ) which, when
used inside a loop, can modify iteration scheme .
statement terminates execution of the current iteration and starts the
subsequent iteration. exit
statement terminates execution of the current iteration and terminates
the loop. If the when
clause is present but the condition is false, the iteration continues normally.
One loop statement may enclose another loop statement; we call it nested
The assert statement tests the boolean condition. If this is false,
it displays a message containing report string and affects the simulation
run if required.
The general structure of assertion clause is:
If the report
clause is omitted the default message is "Assertion
violation". If the severity
clause is present the expression must be of the type severity_level:
If it is omitted, the default is error
. A simulator may terminate execution if an assertion violation
occurs and the severity value is failure or