prepared by P. Bakowski
Contents: entity declaration,
architecture declaration, components,
component instantiation, components
configuration, simple structural descriptions
statement, configuration modules,
user-defined attributes, exercises
The header may include specification of
generic constants. Generics allow to determine some quantitative
aspects of the structure (e.g. size of the bus) and behavior (e.g. number
of counting steps) of the entity.
The potential composition of architecture module comprises:
Basic structural description
A basic structural description is built from interconnected
components. The components must be declared
and configured. Then they can be instantiated.
basic of system
The following example declares a RAM block component with address
depth and data width dependent on generic constants.
This component can act as a template for a RAM entity .
The configuration statement looks as follows:
component declared in the previous page may be instantiated
as (positional association):
(val_real:real) return integer
real; out_int:out int);
signal real_s: real:= 2.74;
signal int_s: integer:= 2;
-- actual_to_formal type conversion
formal_to_actual type conversion
Example of configuration module elaborated for
the full adder description;
The general form of generate
statement is illustrated below:
The general form of block construct
The following example shows an architecture containing only one block.
The signal assignments inside the block are guarded by the condition specified
in the header of the block.
The VHDL blocks may be nested. If
a block is nested inside another one, the internal block activation condition
may be combined with the external block guard.
For example, the above architecture may be embedded into a higher
level block providing an enable (enb)
The enable signal is validated by the state '1'.
Now, the completed architecture may be described as follows:
The modeling solution with register
User attribute declaration
User defined attributes are constants of arbitrary types. Such
constants are associated to attribute specification. They quantify additional
information about an item, for example the capacitance load on ports. Note
that VHDL does not allow any calculation of attribute values. Attributes
may be related to an entity unit, an architecture unit, a configuration
unit, a procedure or function module, a package, a type or subtype, a signal,
a variable, a component, a file, a label, a literal, a unit or a group.
The following is a general form of attribute declaration/specification:
capacitance and drive loading, driver type,
pin numbering, signal arrival time, ...
attribute arrival_time of
clk: signal is 4 ns;
attribute pin_number of
a_bus: signal is "24";
attribute max_freq of
my_FPGA: entity is 10 MHz;
attribute min_power of
my_FPGA: entity is 10 mW;
Timing delays may be modified to correspond to
related to the architecture
attribute max_freq of
my_ASIC: architecture is 10 MHz;
attribute max_size of
my_FPGA: architecture is 100 s_mm
They may be used by a synthesizer to select the required