2

VHDL sequential statements

prepared by P. Bakowski

This page describes the sequential statements of the VHDL language. The sequential statements are used to describe the sequences of operations.
The VHDL sequential statements include well-known programming structures like if else conditional statements, switches and loops.
Contents: Variable Assignment, If statement, Case statement, Loop statement, Next statement, Null statement, Assertions, exercises

Sequential statements

VHDL provides a number of constructs used to  modify the state of objects such as variables. These modifications are the results of variable assignments. The activation of the assignments is decided by control instructions such as if, case and loop. In principle the variable assignments are (or not) executed in a sequential order following the order of writing (typo logical order) and the results of control instructions.
 

Variable assignment

A variable is given a new value using an assignment statement called in VHDL sequential assignment. In the assignment expression the target object and the assigned value must have the same base type.

b_v : bit_vector(4 downto 0);
i_v : integer;
b_v := "10101"; i_v := 678;
In case when  the assignment target is an aggregate,  the value of the expression must be a composite value of the same type as the target aggregate.
 
Control instructions

The majority of traditional control instructions used in programming language is present in VHDL. All of these constructs use conditional expressions providing boolean result ('true' or 'false')
The simplest control instruction is the  if .. then .. end if statement. It may be completed with else (elsif) keywords to allow multiple conditions. More complex constructs such as case - end case or loop - end loop permit to describe multiple tests and loops.
 


if statement

The if statement is used to select one or none of a collection of statements depending on some condition expression Note that conditions are expressions resulting in boolean values.  If the condition is evaluated to true,  the corresponding statement list is executed. Otherwise, if the else clause is present, the else statement list is executed.

..
if test=1 then
        a_v := 1
else
        a_v := 0;
end if;
..

Each if statement must end with a corresponding end if clause.

elsif statement

Multiple conditions can be built with if statement followed by elsif clause(s):

if test=2 then
    a_v := 2
elsif test=1
    a_v := 1;
else
    a_v := 0;
end if;
case statement

The case statement is used to select a collection of statements based on the range of values of a given expression called  selection expression.  The selection must be of discrete type or  a one-dimensional array.

For the matching choice the expression is selected and the statement list executed.
All the choices must be distinct and all values must be represented in the choice lists. If some choice is not specified than the default choice must be indicated through the use of  others keyword.
I

variable codop: bit_vector(2 downto 0);
variable a,b,c: bit;
case codop is
end case;

 
null statement
The null statement may be used to explicitly show that no action is required for a given choice.
 
variable codop: bit_vector(2 downto 0);
variable a,b,c: bit;
case codop is

Iterative control instructions
In many cases a collection of statements need to executed repeatedly/iteratively  for a specific number of steps until some exit or end condition occurs.
VHDL provides iterative control in the form of loop statements.

loop statements

A basic loop statement  is:

The while condition loop iteration scheme allows a test condition to be evaluated before each iteration.
The iteration  proceeds if the test evaluates to true: test for continuation, otherwise the loop statement terminates. The for loop is used to control the exit from the loop based on iterating through some number of values in a given range.
scheme allows a specified number of iterations. The counter object (e.g.  i ) does  not need to be declared as variable but it does not exist outside the loop.
Counter may not be assigned to. VHDL provides two additional statements which, when used inside a loop, can modify  iteration scheme .

exit and next statements

The next statement terminates execution of the current iteration and starts the subsequent iteration. exit statement terminates execution of the current iteration and terminates the loop.
If the when clause is present but the condition is false, the iteration continues normally.

for i in 1 to 50 loop
    next when (i mod 3) = 0;  -- if true skip to next iteration
    bit_table( i):='0';
end loop ;
..
loop
exit when i=5  -- if true terminate the loop
if (a =1) then
    z(i) <='1';
end if;
i := i+1;
end loop;
..
for i in 1 to 100
loop
    a(i) := c(i) - b(i);
exit when a(i)=0;
end loop ;
 

Nested loops
One loop statement may enclose another loop statement; we call it nested loop.

Assertions

The assert statement tests the boolean condition. If this is false, it displays a message containing report string and affects the simulation run if required.
The general structure of assertion clause is:

assert condition
    report message
        severity action;
If the report clause is omitted the default message is  "Assertion violation".

If the severity clause is present the expression must be of the type severity_level: (note, warning, failure, error)  . If it is omitted, the default is error .

A simulator may terminate execution if an assertion violation occurs and the severity value is failure or error.

assert not (r = `1' and s = `1')
report "both r and s are set to `1'"
severity warning;
..
if (clk'event and clk='1')  -- rising edge
    assert d'stable(setup_time)
        report "setup violation"
            severity error;

..
severity level comments
note message for debugging/test  use
warning timing violations or invalid data not affecting the model state, but which could distort the model behavior
failure error in the model itself
error timing violations or invalid data affecting the state of the model

Exercises