--------------------------------------------------------------
-- Copyright 1996 by Doone Publications. All rights reserved.
--
-- Design:  CNT_ASYNC_CLK_DIV16 
-- Name:    Doug Smith
-- Date:    1st June 1996
--
-- Description:
--   Divide by 16 asynchronous ripple counter.
--   Output is a 50% duty cycle clock.
--------------------------------------------------------------
 
library IEEE;
use IEEE.STD_Logic_1164.all;

entity CNT_ASYNC_CLK_DIV16 is
   port (Clock, Reset: in std_logic;
         Y: out std_logic);
end entity CNT_ASYNC_CLK_DIV16;

architecture RTL of CNT_ASYNC_CLK_DIV16 is
   signal Div2, Div4, Div8, Div16: std_logic;
begin
   process (Clock, Reset)
   begin
      if (Reset = '0') then 
         Div2 <= '0';
      elsif rising_edge(Clock) then
         Div2 <= not Div2;
      end if;

      if (Reset = '0') then 
         Div4 <= '0';
      elsif rising_edge(Div2) then
         Div4 <= not Div4;
      end if;

      if (Reset = '0') then 
         Div8 <= '0';
      elsif rising_edge(Div4) then
         Div8 <= not Div8;
      end if;

      if (Reset = '0') then 
         Div16 <= '0';
      elsif rising_edge(Div8) then
         Div16 <= not Div16;
      end if;

      -- Resynchronize back to Clock
      if (Reset = '0') then 
         Y <= '0';
      elsif rising_edge(Clock) then
         Y <= Div16;
      end if;
   end process;
end architecture RTL;