"

" ABEL Code for the Sequence detector 1011,
" implemented as a Mealy Machine with Binary encoding
" File: C:\XLNXEX\STATEED\MyStABL.abl
" created: 05/14/00 18:39:04
" from: 'C:\XLNXEX\STATEED\MyStABL.asf'
" by: fsm2hdl - version: 2.0.1.53
"
module mystabl
Title 'mystabl'
Declarations

"clocks
CLK PIN;

"input ports
RST PIN;
X PIN;

"output ports
Z PIN;

"******** BINARY ENCODED state machine: Sreg0 ******

Sreg0_0 NODE istype 'reg';

xilinx property 'save Sreg0_0';

Sreg0_1 NODE istype 'reg';

xilinx property 'save Sreg0_1';

Sreg0 = [Sreg0_1, Sreg0_0];
S0 = ^b00;
S1 = ^b01;
S2 = ^b10;
S3 = ^b11;

"diagram ACTIONS

"************* state machine: Sreg0 *************

Equations
" clock signals definitions

Sreg0.clk = CLK;
Sreg0_0.clr = RST;
Sreg0_1.clr = RST;

State_diagram Sreg0

State S0:

IF (!X) THEN
S0 WITH Z=^b0;
ENDWITH
ELSE IF (X) THEN
S1 WITH Z=^b0;
ENDWITH;

State S1:

IF (X) THEN
S1 WITH Z=^b0;
ENDWITH
ELSE IF (!X) THEN
S2 WITH Z=^b0;
ENDWITH;

State S2:

IF (X) THEN
S3 WITH Z=^b0;
ENDWITH
ELSE IF (!X) THEN
S0 WITH Z=^b0;
ENDWITH;

State S3:

IF (!X) THEN
S2 WITH Z=^b0;
ENDWITH
ELSE IF (X) THEN
S1 WITH Z=^b1;
ENDWITH;

" end of state machine - Sreg0

end mystabl