EE201 Lab 4

VHDL pre-lab questions

To be submitted online using Mallard

1. Indicate which of the following statements are correct.
• VHDL is a strongly-typed language
• VHDL is a sequential language
• The name of an output port can be: out
• The identifiers “in”, “out”, “and” and “or” can be used to designate signals
• The order of concurrent statements in an architecture body to describe a combinational circuit does not matter for the operation of the circuit

2. A behavioral model describes a circuit in terms of (indicates the correct statements – more than one statement can be correct):
• How gates are interconnected
• The transfer function between the input and output signals
• A combination of both
• None of the above
• A dataflow or algorithmic style.
3. A structural model describes a circuit in terms of:
• How gates are interconnected
• The transfer function between the input and output signals
• A combination of both
• None of the above
• A dataflow model
4. Concurrency in VHDL means (indicate all the correct statements)
• One can run several VHDL programs independently
• Signal assignment statements will be evaluated when one of the signals on the right hand side of the expression changes
• Signal assignments statements will be evaluated in the sequence they occur
• Concurrent signal statement can be executed in parallel
• The textual order of concurrent statements have no effect on the order in which they are executed
• Concurrency capture the parallel nature of digital hardware
5. Consider the following VHDL model

entity MYCRCT is

port (A, B: in std_logic;

Y: out std_logic);

end MYCRCT;

architecture MODEL of MYCRCT is

component NOT1

port (in1: in std_logic;

out1: out std_logic);

component AND2

port (in1, in2: in std_logic;

out1: out std_logic);

end component;

component OR2

port (in1, in2: in std_logic;

out1: out std_logic);

end component;

signal int1, int2, int3, int4: std_logic;

begin

gate0: NOT1 port map (A, int1);

gate1: OR2 port map (int1, C, int2);

gate2: AND2 port map (int1, B, int3);

gate3: AND2 port map (int2, A, int4);

gate4: OR2 port map (int3, int4, Y);

end MODEL;

1. Does the VHDL file describe a behavioral or structural model?
• Behavioral
• Structural
• Combination
2. Give the logic expression of the circuit, as it is implemented by the above model. Your logic expression should reflect the actual circuit described by the VHDL code (i.e. do not simplify the expression). When entering the logic expression use the following rules: (explain here how to enter logic expressions in Mallard)
3. Can you simplify the circuit? Is so, give the simplified sum of product expression

Back to Lab 4; Submit on Mallard.