LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

entity  interface is


  port (
	clk,reset,start    : in     std_logic;                   -- input clock
	di      : in     std_logic_vector(15 downto 0);  
	do      : out    std_logic_vector(15 downto 0);  
        qa,qb   : out    std_logic_vector(15 downto 0);  -- multiplier inputs
        mult_p  : in     std_logic_vector(31 downto 0);  -- multiplier output
        oen     : out std_logic
	);

end interface;


architecture a of interface is

  signal ld_a,ld_b, ld_p :std_logic;  -- input registers for A,B
  signal qp :  std_logic_vector(31 downto 0);  -- multiplier product register

  signal mx_s : std_logic;

  signal pstate, nstate: std_logic_vector(2 downto 0);

  constant STATE_A : std_logic_vector(2 downto 0) := "000";
  constant STATE_B : std_logic_vector(2 downto 0) := "001";
  constant STATE_C : std_logic_vector(2 downto 0) := "011";
  constant STATE_D : std_logic_vector(2 downto 0) := "010";
  constant STATE_E : std_logic_vector(2 downto 0) := "110";
  constant STATE_F : std_logic_vector(2 downto 0) := "100";

begin
  regs:process(clk,reset)
    begin
      if (reset = '0') then
	qa <= "0000000000000000";
	qb <= "0000000000000000";
	pstate <= "000";
      elsif (clk'event and clk='1') then
	if (ld_a = '1') then
	  qa <= di;
	end if;
	if (ld_b = '1') then
	  qb <= di;
	end if;
	if (ld_p = '1') then
	  qp <= mult_p;
	end if;
	pstate <= nstate;
      end if;

   end process regs;

   
  -- mux for do output
  do <=  qp(31 downto 16) when (mx_s = '1') else qp(15 downto 0);

  fsm:process(start,pstate)
    begin

      ld_a <= '0';
      ld_b <= '0';
      ld_p <= '0';
      oen <= '0';
      mx_s <= '0';
      nstate <= pstate;

      case pstate is 
	when STATE_A =>  if (start = '1') then
                            nstate <= STATE_B;
                         end if;
	                
	when STATE_B =>  ld_a <= '1';nstate <= STATE_C;

	when STATE_C =>  ld_b <= '1';nstate <= STATE_D;

	when STATE_D =>  ld_p <= '1';nstate <= STATE_E;
	when STATE_E =>  oen <= '1'; nstate <= STATE_F;
	when STATE_F =>  oen <= '1'; mx_s <= '1';
	    if (start = '0') then
               nstate <= STATE_A;
	    end if;

        when others => nstate <= STATE_A;

      end case;

   end process fsm;

end a;

      







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