Reading /opt/ecad/mentor/pctools/modelsim/default/modeltech/bin/../sunos5/../tcl/vsim/pref.tcl 

# 5.4c

# vsim -do {run 800 ns;quit} -lib sim1 -c cfg_tb 
# //  ModelSim SE/EE VHDL 5.4c Jul 29 2000 SunOS 5.6
# //
# //  Copyright (c) Mentor Graphics Corporation, 1982-2000, All Rights Reserved.
# //                       UNPUBLISHED, LICENSED SOFTWARE.
# //            CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE
# //          PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS.
# //
# //  Copyright (c) Model Technology Incorporated 1990-2000, All Rights Reserved.
# //
# Loading /opt/ecad/mentor/pctools/modelsim/default/modeltech/bin/../sunos5/../std.standard
# Loading /opt/ecad/mentor/pctools/modelsim/default/modeltech/bin/../sunos5/../ieee.std_logic_1164(body)
# Loading /opt/ecad/mentor/pctools/modelsim/default/modeltech/bin/../sunos5/../std.textio(body)
# Loading ../obj/qhdl/utilities.standard_utils(body)
# Loading ../obj/qhdl/utilities.std_logic_1164_utils(body)
# Loading ../obj/qhdl/sim1.cfg_tb
# Loading ../obj/qhdl/sim1.tb(a)
# Loading ../obj/qhdl/sim1.stimfile(behv)
# Loading ../obj/qhdl/sim1.timecheck(behv)
# run 800 ns;quit 
# ** Warning: 
# X value on d
#    Time: 0 ps  Iteration: 0  Instance: /tb/tc
# ** Warning: 
# X value on clk
#    Time: 0 ps  Iteration: 0  Instance: /tb/tc
# ** Warning: 
# 0.02 ns: setup time violation: 0.01 ns < 0.05 ns
# 
#    Time: 20 ps  Iteration: 0  Instance: /tb/tc
# ** Warning: 
# 1.04 ns: clock min pulse width high violation: 0.01 ns < 0.3 ns
# 
#    Time: 1040 ps  Iteration: 0  Instance: /tb/tc
# ** Warning: 
# 1.05 ns: clock min pulse width low violation: 0.01 ns < 0.5 ns
# 
#    Time: 1050 ps  Iteration: 0  Instance: /tb/tc
# ** Warning: 
# 7.52 ns: setup time violation: 0.045 ns < 0.05 ns
# 
#    Time: 7520 ps  Iteration: 0  Instance: /tb/tc
# ** Warning: 
# 9.59 ns: hold time violation: 0.07 ns < 0.075 ns
# 
#    Time: 9590 ps  Iteration: 0  Instance: /tb/tc