Gate Level Implementation.

Here is the gate level implementation of the given multiplexor.

        module multiplexor4_1(out, in1, in2, in3, in4, cntrl1, cntrl2);

          output out;
          input in1, in2, in3, in4, cntrl1, cntrl2;
          wire notcntlr1, notcntrl2, w, x, y, z;

          not (notcntrl1, cntrl1);
          not (notcntrl2, cntrl2);

          and (w, in1, notcntrl1, notcntrl2);
          and (x, in2, notcntrl1, cntrl2);
          and (y, in3, cntrl1, notcntrl2);
          and (z, in4, cntrl1, cntrl2);

          or (out, w, x, y, z);

        endmodule

Now we break up the code and go through it line by line.

         module multiplexor4_1(out, in1, in2, in3, in4, cntrl1, cntrl2);

The first line of any module description is the keyword module followed by the module name by which it can be referenced. Then the port list, this is all that can be seen from outside the module. The order of the port list is conventionally output first.

The line is ended with a semicolon, this may seem strange to C programmers but is required in Verilog.

        output out;
        input in1, in2, in3, in4, cntrl1, cntrl2;

All the ports in the port list must be declared as input, output or inout, these are then assumed to be wire data types unless declared otherwise. When declared as wire Verilog expects a implicit assignment to the output and values to be driven into the inputs by an external module.

        wire notcntrl1, notcntrl2, w, x, y, z;

This declares the internal wires, these represent connections between hardware elements. Values are driven onto them by the output of the devices to whicih they are connected.

        not (notcntrl1, cntrl1);
        not (notcntrl2, cntrl2);

If you look are the logic diagram, it is clear what is happening here. This is a description of a not gate, the output is notcntrl1 and the input is cntrl1. Note the gate has no name, naming is not compulsory for predefined gates provided by verilog. Earlier we said that a value will be driven into notcntrl1, this is what the not gate does; everytime the value of the input, cntrl1 changes, the value of notcntrl1 is updated automatically.

          and (w, in1, notcntrl1, notcntrl2);
          and (x, in2, notcntrl1, cntrl2);
          and (y, in3, cntrl1, notcntrl2);
          and (z, in4, cntrl1, cntrl2);

          or (out, w, x, y, z);

These drive the values into w, x, y and z respectively in the same way described above. The connections in the logic diagram can be used to verify the connection are correct. Note: each line ends with a semicolon (;).
endmodule
The end of a module is indicated by the keyword endmodule.

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